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adding input buffering to bus arbiters to reduce backpressure delay propagation

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This commit is contained in:
Blaise Tine
2020-12-05 17:31:29 -08:00
parent 13a5370254
commit d0f2a3984d
17 changed files with 480 additions and 338 deletions
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96
hw/rtl/VX_csr_io_arb.v
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@@ -14,39 +14,39 @@ module VX_csr_io_arb #(
input wire [REQS_BITS-1:0] request_id,
// input requests
input wire csr_io_req_valid_in,
input wire [ADDR_WIDTH-1:0] csr_io_req_addr_in,
input wire csr_io_req_rw_in,
input wire [DATA_WIDTH-1:0] csr_io_req_data_in,
output wire csr_io_req_ready_in,
// output request
output wire [NUM_REQS-1:0] csr_io_req_valid_out,
output wire [NUM_REQS-1:0][ADDR_WIDTH-1:0] csr_io_req_addr_out,
output wire [NUM_REQS-1:0] csr_io_req_rw_out,
output wire [NUM_REQS-1:0][DATA_WIDTH-1:0] csr_io_req_data_out,
input wire [NUM_REQS-1:0] csr_io_req_ready_out,
// input response
input wire [NUM_REQS-1:0] csr_io_rsp_valid_in,
input wire [NUM_REQS-1:0][DATA_WIDTH-1:0] csr_io_rsp_data_in,
output wire [NUM_REQS-1:0] csr_io_rsp_ready_in,
input wire req_valid_in,
input wire [ADDR_WIDTH-1:0] req_addr_in,
input wire req_rw_in,
input wire [DATA_WIDTH-1:0] req_data_in,
output wire req_ready_in,
// output response
output wire csr_io_rsp_valid_out,
output wire [DATA_WIDTH-1:0] csr_io_rsp_data_out,
input wire csr_io_rsp_ready_out
output wire rsp_valid_out,
output wire [DATA_WIDTH-1:0] rsp_data_out,
input wire rsp_ready_out,
// output request
output wire [NUM_REQS-1:0] req_valid_out,
output wire [NUM_REQS-1:0][ADDR_WIDTH-1:0] req_addr_out,
output wire [NUM_REQS-1:0] req_rw_out,
output wire [NUM_REQS-1:0][DATA_WIDTH-1:0] req_data_out,
input wire [NUM_REQS-1:0] req_ready_out,
// input response
input wire [NUM_REQS-1:0] rsp_valid_in,
input wire [NUM_REQS-1:0][DATA_WIDTH-1:0] rsp_data_in,
output wire [NUM_REQS-1:0] rsp_ready_in
);
if (NUM_REQS > 1) begin
for (genvar i = 0; i < NUM_REQS; i++) begin
assign csr_io_req_valid_out[i] = csr_io_req_valid_in && (request_id == `REQS_BITS'(i));
assign csr_io_req_addr_out[i] = csr_io_req_addr_in;
assign csr_io_req_rw_out[i] = csr_io_req_rw_in;
assign csr_io_req_data_out[i] = csr_io_req_data_in;
assign req_valid_out[i] = req_valid_in && (request_id == `REQS_BITS'(i));
assign req_addr_out[i] = req_addr_in;
assign req_rw_out[i] = req_rw_in;
assign req_data_out[i] = req_data_in;
end
assign csr_io_req_ready_in = csr_io_req_ready_out[request_id];
assign req_ready_in = req_ready_out[request_id];
end else begin
@@ -54,29 +54,49 @@ module VX_csr_io_arb #(
`UNUSED_VAR (reset)
`UNUSED_VAR (request_id)
assign csr_io_req_valid_out = csr_io_req_valid_in;
assign csr_io_req_addr_out = csr_io_req_addr_in;
assign csr_io_req_rw_out = csr_io_req_rw_in;
assign csr_io_req_data_out = csr_io_req_data_in;
assign csr_io_req_ready_in = csr_io_req_ready_out;
assign req_valid_out = req_valid_in;
assign req_addr_out = req_addr_in;
assign req_rw_out = req_rw_in;
assign req_data_out = req_data_in;
assign req_ready_in = req_ready_out;
end
///////////////////////////////////////////////////////////////////////
// Inputs buffering
wire [NUM_REQS-1:0] rsp_valid_in_qual;
wire [NUM_REQS-1:0][DATA_WIDTH-1:0] rsp_data_in_qual;
wire [NUM_REQS-1:0] rsp_ready_in_qual;
for (genvar i = 0; i < NUM_REQS; ++i) begin
VX_skid_buffer #(
.DATAW (DATA_WIDTH),
.PASSTHRU (NUM_REQS < 4)
) rsp_buffer (
.clk (clk),
.reset (reset),
.valid_in (rsp_valid_in[i]),
.data_in (rsp_data_in[i]),
.ready_in (rsp_ready_in[i]),
.valid_out (rsp_valid_in_qual[i]),
.data_out (rsp_data_in_qual[i]),
.ready_out (rsp_ready_in_qual[i])
);
end
VX_stream_arbiter #(
.NUM_REQS(NUM_REQS),
.DATAW(DATA_WIDTH),
.BUFFERED(NUM_REQS >= 4)
) rsp_arb (
.clk (clk),
.reset (reset),
.valid_in (csr_io_rsp_valid_in),
.valid_out (csr_io_rsp_valid_out),
.data_in (csr_io_rsp_data_in),
.data_out (csr_io_rsp_data_out),
.ready_in (csr_io_rsp_ready_in),
.ready_out (csr_io_rsp_ready_out)
.clk (clk),
.reset (reset),
.valid_in (rsp_valid_in_qual),
.data_in (rsp_data_in_qual),
.ready_in (rsp_ready_in_qual),
.valid_out (rsp_valid_out),
.data_out (rsp_data_out),
.ready_out (rsp_ready_out)
);
endmodule