diff --git a/.DS_Store b/.DS_Store index ffe5b8b3..32aaf96e 100644 Binary files a/.DS_Store and b/.DS_Store differ diff --git a/rtl/Makefile b/rtl/Makefile new file mode 100644 index 00000000..aa0ca37e --- /dev/null +++ b/rtl/Makefile @@ -0,0 +1,12 @@ + + + +all: RUNFILE + + +VERILATOR: + verilator -Wall -cc vortex.v VX_f_d_reg.v VX_fetch.v --exe test_bench.cpp + +RUNFILE: VERILATOR + (cd obj_dir && make -j -f Vvortex.mk) + diff --git a/rtl/VX_decode.v b/rtl/VX_decode.v new file mode 100644 index 00000000..afdeeda8 --- /dev/null +++ b/rtl/VX_decode.v @@ -0,0 +1,386 @@ + + +`define R_INST 7'd51 +`define L_INST 7'd3 +`define ALU_INST 7'd19 +`define S_INST 7'd35 +`define B_INST 7'd99 +`define LUI_INST 7'd55 +`define AUIPC_INST 7'd23 +`define JAL_INST 7'd111 +`define JALR_INST 7'd103 +`define SYS_INST 7'd115 + + +`define WB_ALU 2'h1 +`define WB_MEM 2'h2 +`define WB_JAL 2'h3 +`define NO_WB 2'h0 + + +`define RS2_IMMED 1 +`define RS2_REG 0 + + +`define NO_MEM_READ 3'h7 +`define LB_MEM_READ 3'h0 +`define LH_MEM_READ 3'h1 +`define LW_MEM_READ 3'h2 +`define LBU_MEM_READ 3'h4 +`define LHU_MEM_READ 3'h5 + + +`define NO_MEM_WRITE 3'h7 +`define SB_MEM_WRITE 3'h0 +`define SH_MEM_WRITE 3'h1 +`define SW_MEM_WRITE 3'h2 + + +`define NO_BRANCH 3'h0 +`define BEQ 3'h1 +`define BNE 3'h2 +`define BLT 3'h3 +`define BGT 3'h4 +`define BLTU 3'h5 +`define BGTU 3'h6 + + +`define NO_ALU 4'd15 +`define ADD 4'd0 +`define SUB 4'd1 +`define SLLA 4'd2 +`define SLT 4'd3 +`define SLTU 4'd4 +`define XOR 4'd5 +`define SRL 4'd6 +`define SRA 4'd7 +`define OR 4'd8 +`define AND 4'd9 +`define SUBU 4'd10 +`define LUI_ALU 4'd11 +`define AUIPC_ALU 4'd12 +`define CSR_ALU_RW 4'd13 +`define CSR_ALU_RS 4'd14 +`define CSR_ALU_RC 4'd15 + +module VX_decode( + // Fetch Inputs + input wire clk, + input wire[31:0] in_instruction, + input wire[31:0] in_curr_PC, + // WriteBack inputs + input wire[31:0] in_write_data, + input wire[4:0] in_rd, + input wire[1:0] in_wb, + + // FORWARDING INPUTS + input wire in_src1_fwd, + input wire[31:0] in_src1_fwd_data, + input wire in_src2_fwd, + input wire[31:0] in_src2_fwd_data, + + output wire[11:0] out_csr_address, // done + output wire out_is_csr, // done + output wire[31:0] out_csr_mask, // done + + // Outputs + output wire[4:0] out_rd, + output wire[4:0] out_rs1, + output wire[31:0] out_rd1, + output wire[4:0] out_rs2, + output wire[31:0] out_rd2, + output wire[1:0] out_wb, + output wire[3:0] out_alu_op, + output wire out_rs2_src, // NEW + output reg[31:0] out_itype_immed, // new + output wire[2:0] out_mem_read, // NEW + output wire[2:0] out_mem_write, // NEW + output reg[2:0] out_branch_type, + output reg out_branch_stall, + output reg out_jal, + output reg[31:0] out_jal_offset, + output reg[19:0] out_upper_immed, + output wire[31:0] out_PC_next +); + + wire[6:0] curr_opcode; + + reg[3:0] alu_op; + + wire[31:0] rd1_register; + wire[31:0] rd2_register; + + wire is_itype; + wire is_rtype; + wire is_stype; + wire is_btype; + wire is_linst; + wire is_jal; + wire is_jalr; + wire is_lui; + wire is_auipc; + wire is_csr; + wire is_csr_immed; + wire is_e_inst; + + wire write_register; + + wire[2:0] func3; + wire[6:0] func7; + wire[11:0] u_12; + + + wire[7:0] jal_b_19_to_12; + wire jal_b_11; + wire[9:0] jal_b_10_to_1; + wire jal_b_20; + wire jal_b_0; + wire[20:0] jal_unsigned_offset; + wire[31:0] jal_1_offset; + + wire[11:0] jalr_immed; + wire[31:0] jal_2_offset; + + wire jal_sys_cond1; + wire jal_sys_cond2; + wire jal_sys_jal; + wire[31:0] jal_sys_off; + + wire csr_cond1; + wire csr_cond2; + + wire[11:0] alu_tempp; + wire alu_shift_i; + wire[11:0] alu_shift_i_immed; + + wire[1:0] csr_type; + reg[3:0] csr_alu; + + VX_register_file vx_register_file( + .clk(clk), + .in_write_register(write_register), + .in_rd(in_rd), + .in_data(in_write_data), + .in_src1(out_rs1), + .in_src2(out_rs2), + .out_src1_data(rd1_register), + .out_src2_data(rd2_register) + ); + + assign write_register = (in_wb != 2'h0) ? (1'b1) : (1'b0); + assign curr_opcode = in_instruction[6:0]; + + + assign out_rd = in_instruction[11:7]; + assign out_rs1 = in_instruction[19:15]; + assign out_rs2 = in_instruction[24:20]; + assign func3 = in_instruction[14:12]; + assign func7 = in_instruction[31:25]; + assign u_12 = in_instruction[31:20]; + + + assign out_PC_next = in_curr_PC + 32'h4; + + + // Write Back sigal + assign is_rtype = (curr_opcode == `R_INST); + assign is_linst = (curr_opcode == `L_INST); + assign is_itype = (curr_opcode == `ALU_INST) || is_linst; + assign is_stype = (curr_opcode == `S_INST); + assign is_btype = (curr_opcode == `B_INST); + assign is_jal = (curr_opcode == `JAL_INST); + assign is_jalr = (curr_opcode == `JALR_INST); + assign is_lui = (curr_opcode == `LUI_INST); + assign is_auipc = (curr_opcode == `AUIPC_INST); + assign is_csr = (curr_opcode == `SYS_INST) && (func3 != 0); + assign is_csr_immed = (is_csr) && (func3[2] == 1); + assign is_e_inst = (curr_opcode == `SYS_INST) && (func3 == 0); + + + // ch_print("DECODE: PC: {0}, INSTRUCTION: {1}", in_curr_PC, in_instruction); + + + assign out_rd1 = (is_jal == 1'b1) ? in_curr_PC : + ((in_src1_fwd == 1'b1) ? in_src1_fwd_data : rd1_register); + + assign out_rd2 = (in_src2_fwd == 1'b1) ? in_src2_fwd_data : rd2_register; + + + + assign out_is_csr = is_csr; + assign out_csr_mask = (is_csr_immed == 1'b1) ? {27'h0, out_rs1} : out_rd1; + + + assign out_wb = (is_jal || is_jalr || is_e_inst) ? `WB_JAL : + is_linst ? `WB_MEM : + (is_itype || is_rtype || is_lui || is_auipc || is_csr) ? `WB_ALU : + `NO_WB; + + + assign out_rs2_src = (is_itype || is_stype) ? `RS2_IMMED : `RS2_REG; + + // MEM signals + assign out_mem_read = (is_linst) ? func3 : `NO_MEM_READ; + assign out_mem_write = (is_stype) ? func3 : `NO_MEM_WRITE; + + // UPPER IMMEDIATE + always @(*) begin + case(curr_opcode) + `LUI_INST: out_upper_immed = {func7, out_rs2, out_rs1, func3}; + `AUIPC_INST: out_upper_immed = {func7, out_rs2, out_rs1, func3}; + default: out_upper_immed = 20'h0; + endcase // curr_opcode + end + + + assign jal_b_19_to_12 = in_instruction[19:12]; + assign jal_b_11 = in_instruction[20]; + assign jal_b_10_to_1 = in_instruction[30:21]; + assign jal_b_20 = in_instruction[31]; + assign jal_b_0 = 1'b0; + assign jal_unsigned_offset = {jal_b_20, jal_b_19_to_12, jal_b_11, jal_b_10_to_1, jal_b_0}; + assign jal_1_offset = {{11{jal_b_20}}, jal_unsigned_offset}; + + + assign jalr_immed = {func7, out_rs2}; + assign jal_2_offset = {{20{jalr_immed[11]}}, jalr_immed}; + + + assign jal_sys_cond1 = func3 == 3'h0; + assign jal_sys_cond2 = u_12 < 12'h2; + + assign jal_sys_jal = (jal_sys_cond1 && jal_sys_cond2) ? 1'b1 : 1'b0; + assign jal_sys_off = (jal_sys_cond1 && jal_sys_cond2) ? 32'hb0000000 : 32'hdeadbeef; + + // JAL + always @(*) begin + case(curr_opcode) + `JAL_INST: + begin + out_jal = 1'b1; + out_jal_offset = jal_1_offset; + end + `JALR_INST: + begin + out_jal = 1'b1; + out_jal_offset = jal_2_offset; + end + `SYS_INST: + begin + out_jal = jal_sys_jal; + out_jal_offset = jal_sys_off; + end + default: + begin + out_jal = 1'b0; + out_jal_offset = 32'hdeadbeef; + end + endcase + end + + + // CSR + + assign csr_cond1 = func3 != 3'h0; + assign csr_cond2 = u_12 >= 12'h2; + + assign out_csr_address = (csr_cond1 && csr_cond2) ? u_12 : 12'h55; + + + // ITYPE IMEED + assign alu_shift_i = (func3 == 3'h1) || (func3 == 3'h5); + assign alu_shift_i_immed = {{7{1'b0}}, out_rs2}; + assign alu_tempp = alu_shift_i ? alu_shift_i_immed : u_12; + + + always @(*) begin + case(curr_opcode) + `ALU_INST: out_itype_immed = {{20{alu_tempp[11]}}, alu_tempp}; + `S_INST: out_itype_immed = {{20{func7[6]}}, func7, out_rd}; + `L_INST: out_itype_immed = {{20{u_12[11]}}, u_12}; + `B_INST: out_itype_immed = {{20{in_instruction[31]}}, in_instruction[31], in_instruction[7], in_instruction[30:25], in_instruction[11:8]}; + default: out_itype_immed = 32'hdeadbeef; + endcase + end + + + always @(*) begin + case(curr_opcode) + `B_INST: + begin + out_branch_stall = 1'b1; + case(func3) + 3'h0: out_branch_type = `BEQ; + 3'h1: out_branch_type = `BNE; + 3'h4: out_branch_type = `BLT; + 3'h5: out_branch_type = `BGT; + 3'h6: out_branch_type = `BLTU; + 3'h7: out_branch_type = `BGTU; + default: out_branch_type = `NO_BRANCH; + endcase + end + + `JAL_INST: + begin + out_branch_type = `NO_BRANCH; + out_branch_stall = 1'b1; + end + `JALR_INST: + begin + out_branch_type = `NO_BRANCH; + out_branch_stall = 1'b1; + end + default: + begin + out_branch_type = `NO_BRANCH; + out_branch_stall = 1'b0; + end + endcase + end + + + always @(*) begin + // ALU OP + case(func3) + 3'h0: alu_op = (curr_opcode == `ALU_INST) ? `ADD : (func7 == 7'h0 ? `ADD : `SUB); + 3'h1: alu_op = `SLLA; + 3'h2: alu_op = `SLT; + 3'h3: alu_op = `SLTU; + 3'h4: alu_op = `XOR; + 3'h5: alu_op = (func7 == 7'h0) ? `SRL : `SRA; + 3'h6: alu_op = `OR; + 3'h7: alu_op = `AND; + default: alu_op = `NO_ALU; + endcase + end + + + assign csr_type = func3[1:0]; + + always @(*) begin + case(csr_type) + 2'h1: csr_alu = `CSR_ALU_RW; + 2'h2: csr_alu = `CSR_ALU_RS; + 2'h3: csr_alu = `CSR_ALU_RC; + default: csr_alu = `NO_ALU; + endcase + end + + + assign out_alu_op = is_btype ? ((out_branch_type < `BLTU) ? `SUB : `SUBU) : + is_lui ? `LUI_ALU : + is_auipc ? `AUIPC_ALU : + is_csr ? csr_alu : + (is_stype || is_linst) ? `ADD : + alu_op; + + +endmodule + + + + + + + + diff --git a/rtl/VX_f_d_reg.v b/rtl/VX_f_d_reg.v new file mode 100644 index 00000000..27b8a1a9 --- /dev/null +++ b/rtl/VX_f_d_reg.v @@ -0,0 +1,45 @@ + + + +module VX_f_d_reg ( + input wire clk, + input wire reset, + input wire[31:0] in_instruction, + input wire in_valid, + input wire[31:0] in_curr_PC, + input wire in_fwd_stall, + input wire in_freeze, + output wire[31:0] out_instruction, + output wire[31:0] out_curr_PC, + output wire out_valid +); + + always @(posedge clk) begin + $display("Fetch Inst: %d\tDecode Inst: %d", in_instruction, out_instruction); + end + + reg[31:0] instruction; + reg[31:0] curr_PC; + reg valid; + + + always @(posedge clk or posedge reset) begin + if(reset || (in_fwd_stall == 1'b1) || (in_freeze == 1'b1)) begin + instruction <= 32'h0; + curr_PC <= 32'h0; + valid <= 1'b0; + end else begin + instruction <= in_instruction; + valid <= in_valid; + curr_PC <= in_curr_PC; + end + end + + + assign out_instruction = instruction; + assign out_curr_PC = curr_PC; + assign out_valid = valid; + + + +endmodule \ No newline at end of file diff --git a/rtl/VX_fetch.v b/rtl/VX_fetch.v new file mode 100644 index 00000000..7bf3a35b --- /dev/null +++ b/rtl/VX_fetch.v @@ -0,0 +1,168 @@ + + +module VX_fetch ( + input wire clk, + input wire reset, + input wire in_branch_dir, + input wire in_freeze, + input wire[31:0] in_branch_dest, + input wire in_branch_stall, + input wire in_fwd_stall, + input wire in_branch_stall_exe, + input wire in_jal, + input wire[31:0] in_jal_dest, + input wire in_interrupt, + input wire in_debug, + input wire[31:0] in_instruction, + + output wire[31:0] out_instruction, + output wire out_delay, + output wire[31:0] out_curr_PC, + output wire out_valid +); + + + reg stall_reg; + reg delay_reg; + reg[31:0] old; + reg[4:0] state; + reg[31:0] real_PC; + reg[31:0] JAL_reg; + reg[31:0] BR_reg; + reg prev_debug; + + + reg delay; + reg[31:0] PC_to_use; + reg[31:0] PC_to_use_temp; + reg stall; + reg[31:0] temp_PC; + reg[31:0] out_PC; + reg[4:0] temp_state; + reg[4:0] tempp_state; + + initial begin + stall_reg = 0; + delay_reg = 0; + old = 0; + state = 0; + real_PC = 0; + JAL_reg = 0; + BR_reg = 0; + prev_debug = 0; + end + + always @(*) begin + case(state) + 5'h00: PC_to_use_temp = real_PC; + 5'h01: PC_to_use_temp = JAL_reg; + 5'h02: PC_to_use_temp = BR_reg; + 5'h03: PC_to_use_temp = real_PC; + 5'h04: PC_to_use_temp = old; + default: PC_to_use_temp = 32'h0; + endcase // state + end + + + + assign out_delay = 0; + assign delay = out_delay; + + always @(*) begin + if ((delay_reg == 1'b1) && (in_freeze == 1'b0)) begin + PC_to_use = old; + end else if (in_debug == 1'b1) begin + if (prev_debug == 1'b1) begin + PC_to_use = old; + end else begin + PC_to_use = real_PC; + end + end else if (stall_reg == 1'b1) begin + PC_to_use = old; + end else begin + PC_to_use = PC_to_use_temp; + end + end + + + assign stall = in_branch_stall || in_fwd_stall || in_branch_stall_exe || in_interrupt || delay || in_freeze; + + assign out_instruction = stall ? 32'b0 : in_instruction; + assign out_valid = stall ? 1'b0 : 1'b1; + + + always @(*) begin + + if ((in_jal == 1'b1) && (delay_reg == 1'b0)) begin + temp_PC = in_jal_dest; + end else if ((in_branch_dir == 1'b1) && (delay_reg == 1'b0)) begin + temp_PC = in_branch_dest; + end else begin + temp_PC = PC_to_use; + end + + end + + assign out_PC = temp_PC; + + always @(*) begin + + if (in_jal == 1'b1) begin + temp_state = 5'h1; + end else if (in_branch_dir == 1'b1) begin + temp_state = 5'h2; + end else begin + temp_state = 5'h0; + end + end + + + + + + assign tempp_state = in_interrupt ? 5'h3 : temp_state; + + assign out_curr_PC = out_PC; + + + always @(posedge clk or posedge reset) begin + if(reset) begin + state <= 0; + stall_reg <= 0; + delay_reg <= 0; + old <= 0; + real_PC <= 0; + JAL_reg <= 0; + BR_reg <= 0; + prev_debug <= 0; + + end else begin + + if (in_debug == 1'b1) begin + state <= 5'h3; + end else begin + if (prev_debug == 1'b1) begin + state <= 5'h4; + end else begin + state <= tempp_state; + end + end + + stall_reg <= stall; + delay_reg <= delay || in_freeze; + old <= out_PC; + real_PC <= PC_to_use + 32'h4; + JAL_reg <= in_jal_dest + 32'h4; + BR_reg <= in_branch_dest + 32'h4; + prev_debug <= in_debug; + + end + end + + + + + + + +endmodule \ No newline at end of file diff --git a/rtl/VX_register_file.v b/rtl/VX_register_file.v new file mode 100644 index 00000000..0754d172 --- /dev/null +++ b/rtl/VX_register_file.v @@ -0,0 +1,40 @@ + + +module VX_register_file ( + input wire clk, + input wire in_write_register, + input wire[4:0] in_rd, + input wire[31:0] in_data, + input wire[4:0] in_src1, + input wire[4:0] in_src2, + + output wire[31:0] out_src1_data, + output wire[31:0] out_src2_data +); + + reg[31:0] registers[31:0]; + + wire[31:0] write_data; + + wire[4:0] write_register; + + wire write_enable; + + + + assign write_data = in_data; + assign write_register = in_rd; + + assign write_enable = in_write_register && (in_rd != 5'h0); + + always @(posedge clk) begin + if(write_enable) begin + registers[write_register] <= write_data; + end + end + + assign out_src1_data = registers[in_src1]; + assign out_src2_data = registers[in_src2]; + + +endmodule diff --git a/rtl/obj_dir/VVX_decode.cpp b/rtl/obj_dir/VVX_decode.cpp new file mode 100644 index 00000000..8cdd345f --- /dev/null +++ b/rtl/obj_dir/VVX_decode.cpp @@ -0,0 +1,975 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Design implementation internals +// See VVX_decode.h for the primary calling header + +#include "VVX_decode.h" +#include "VVX_decode__Syms.h" + + +//-------------------- +// STATIC VARIABLES + + +//-------------------- + +VL_CTOR_IMP(VVX_decode) { + VVX_decode__Syms* __restrict vlSymsp = __VlSymsp = new VVX_decode__Syms(this, name()); + VVX_decode* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Reset internal values + + // Reset structure values + _ctor_var_reset(); +} + +void VVX_decode::__Vconfigure(VVX_decode__Syms* vlSymsp, bool first) { + if (0 && first) {} // Prevent unused + this->__VlSymsp = vlSymsp; +} + +VVX_decode::~VVX_decode() { + delete __VlSymsp; __VlSymsp=NULL; +} + +//-------------------- + + +void VVX_decode::eval() { + VL_DEBUG_IF(VL_DBG_MSGF("+++++TOP Evaluate VVX_decode::eval\n"); ); + VVX_decode__Syms* __restrict vlSymsp = this->__VlSymsp; // Setup global symbol table + VVX_decode* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; +#ifdef VL_DEBUG + // Debug assertions + _eval_debug_assertions(); +#endif // VL_DEBUG + // Initialize + if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) _eval_initial_loop(vlSymsp); + // Evaluate till stable + int __VclockLoop = 0; + QData __Vchange = 1; + do { + VL_DEBUG_IF(VL_DBG_MSGF("+ Clock loop\n");); + _eval(vlSymsp); + if (VL_UNLIKELY(++__VclockLoop > 100)) { + // About to fail, so enable debug to see what's not settling. + // Note you must run make with OPT=-DVL_DEBUG for debug prints. + int __Vsaved_debug = Verilated::debug(); + Verilated::debug(1); + __Vchange = _change_request(vlSymsp); + Verilated::debug(__Vsaved_debug); + VL_FATAL_MT(__FILE__,__LINE__,__FILE__,"Verilated model didn't converge"); + } else { + __Vchange = _change_request(vlSymsp); + } + } while (VL_UNLIKELY(__Vchange)); +} + +void VVX_decode::_eval_initial_loop(VVX_decode__Syms* __restrict vlSymsp) { + vlSymsp->__Vm_didInit = true; + _eval_initial(vlSymsp); + // Evaluate till stable + int __VclockLoop = 0; + QData __Vchange = 1; + do { + _eval_settle(vlSymsp); + _eval(vlSymsp); + if (VL_UNLIKELY(++__VclockLoop > 100)) { + // About to fail, so enable debug to see what's not settling. + // Note you must run make with OPT=-DVL_DEBUG for debug prints. + int __Vsaved_debug = Verilated::debug(); + Verilated::debug(1); + __Vchange = _change_request(vlSymsp); + Verilated::debug(__Vsaved_debug); + VL_FATAL_MT(__FILE__,__LINE__,__FILE__,"Verilated model didn't DC converge"); + } else { + __Vchange = _change_request(vlSymsp); + } + } while (VL_UNLIKELY(__Vchange)); +} + +//-------------------- +// Internal Methods + +VL_INLINE_OPT void VVX_decode::_combo__TOP__1(VVX_decode__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_decode::_combo__TOP__1\n"); ); + VVX_decode* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->out_PC_next = ((IData)(4U) + vlTOPp->in_curr_PC); + vlTOPp->out_mem_read = (7U & ((3U == (0x7fU & vlTOPp->in_instruction)) + ? (vlTOPp->in_instruction + >> 0xcU) : 7U)); + vlTOPp->out_mem_write = (7U & ((0x23U == (0x7fU + & vlTOPp->in_instruction)) + ? (vlTOPp->in_instruction + >> 0xcU) : 7U)); + // ALWAYS at VX_decode.v:247 + vlTOPp->out_jal = ((0x6fU == (0x7fU & vlTOPp->in_instruction)) + | ((0x67U == (0x7fU & vlTOPp->in_instruction)) + | ((0x73U == (0x7fU & vlTOPp->in_instruction)) + & ((0U == (7U & (vlTOPp->in_instruction + >> 0xcU))) + & (2U > (0xfffU & (vlTOPp->in_instruction + >> 0x14U))))))); + vlTOPp->out_csr_address = (0xfffU & (((0U != (7U + & (vlTOPp->in_instruction + >> 0xcU))) + & (2U <= + (0xfffU + & (vlTOPp->in_instruction + >> 0x14U)))) + ? (vlTOPp->in_instruction + >> 0x14U) + : 0x55U)); + // ALWAYS at VX_decode.v:306 + vlTOPp->out_branch_stall = ((0x63U == (0x7fU & vlTOPp->in_instruction)) + | ((0x6fU == (0x7fU + & vlTOPp->in_instruction)) + | (0x67U == (0x7fU + & vlTOPp->in_instruction)))); + vlTOPp->out_rd = (0x1fU & (vlTOPp->in_instruction + >> 7U)); + // ALWAYS at VX_decode.v:306 + vlTOPp->out_branch_type = ((0x63U == (0x7fU & vlTOPp->in_instruction)) + ? ((0x4000U & vlTOPp->in_instruction) + ? ((0x2000U & vlTOPp->in_instruction) + ? ((0x1000U + & vlTOPp->in_instruction) + ? 6U : 5U) + : ((0x1000U + & vlTOPp->in_instruction) + ? 4U : 3U)) + : ((0x2000U & vlTOPp->in_instruction) + ? 0U : ((0x1000U + & vlTOPp->in_instruction) + ? 2U + : 1U))) + : 0U); + vlTOPp->VX_decode__DOT__is_itype = ((0x13U == (0x7fU + & vlTOPp->in_instruction)) + | (3U == (0x7fU + & vlTOPp->in_instruction))); + vlTOPp->VX_decode__DOT__is_csr = ((0x73U == (0x7fU + & vlTOPp->in_instruction)) + & (0U != (7U + & (vlTOPp->in_instruction + >> 0xcU)))); + vlTOPp->out_rs1 = (0x1fU & (vlTOPp->in_instruction + >> 0xfU)); + vlTOPp->out_rs2 = (0x1fU & (vlTOPp->in_instruction + >> 0x14U)); + vlTOPp->out_rs2_src = (1U & (((IData)(vlTOPp->VX_decode__DOT__is_itype) + | (0x23U == (0x7fU + & vlTOPp->in_instruction))) + ? 1U : 0U)); + vlTOPp->out_is_csr = vlTOPp->VX_decode__DOT__is_csr; + vlTOPp->out_wb = ((((0x6fU == (0x7fU & vlTOPp->in_instruction)) + | (0x67U == (0x7fU & vlTOPp->in_instruction))) + | ((0x73U == (0x7fU & vlTOPp->in_instruction)) + & (0U == (7U & (vlTOPp->in_instruction + >> 0xcU))))) + ? 3U : ((3U == (0x7fU & vlTOPp->in_instruction)) + ? 2U : ((((((IData)(vlTOPp->VX_decode__DOT__is_itype) + | (0x33U + == (0x7fU + & vlTOPp->in_instruction))) + | (0x37U + == (0x7fU + & vlTOPp->in_instruction))) + | (0x17U + == (0x7fU + & vlTOPp->in_instruction))) + | (IData)(vlTOPp->VX_decode__DOT__is_csr)) + ? 1U : 0U))); + vlTOPp->out_alu_op = ((0x63U == (0x7fU & vlTOPp->in_instruction)) + ? ((5U > (IData)(vlTOPp->out_branch_type)) + ? 1U : 0xaU) : ((0x37U + == + (0x7fU + & vlTOPp->in_instruction)) + ? 0xbU + : ( + (0x17U + == + (0x7fU + & vlTOPp->in_instruction)) + ? 0xcU + : + ((IData)(vlTOPp->VX_decode__DOT__is_csr) + ? + ((1U + == + (3U + & (vlTOPp->in_instruction + >> 0xcU))) + ? 0xdU + : + ((2U + == + (3U + & (vlTOPp->in_instruction + >> 0xcU))) + ? 0xeU + : 0xfU)) + : + (((0x23U + == + (0x7fU + & vlTOPp->in_instruction)) + | (3U + == + (0x7fU + & vlTOPp->in_instruction))) + ? 0U + : + ((0x4000U + & vlTOPp->in_instruction) + ? + ((0x2000U + & vlTOPp->in_instruction) + ? + ((0x1000U + & vlTOPp->in_instruction) + ? 9U + : 8U) + : + ((0x1000U + & vlTOPp->in_instruction) + ? + ((0U + == + (0x7fU + & (vlTOPp->in_instruction + >> 0x19U))) + ? 6U + : 7U) + : 5U)) + : + ((0x2000U + & vlTOPp->in_instruction) + ? + ((0x1000U + & vlTOPp->in_instruction) + ? 4U + : 3U) + : + ((0x1000U + & vlTOPp->in_instruction) + ? 2U + : + ((0x13U + == + (0x7fU + & vlTOPp->in_instruction)) + ? 0U + : + ((0U + == + (0x7fU + & (vlTOPp->in_instruction + >> 0x19U))) + ? 0U + : 1U)))))))))); + // ALWAYS at VX_decode.v:201 + vlTOPp->out_upper_immed = ((0x37U == (0x7fU & vlTOPp->in_instruction)) + ? ((0xfe000U & (vlTOPp->in_instruction + >> 0xcU)) + | (((IData)(vlTOPp->out_rs2) + << 8U) | (((IData)(vlTOPp->out_rs1) + << 3U) + | (7U + & (vlTOPp->in_instruction + >> 0xcU))))) + : ((0x17U == (0x7fU + & vlTOPp->in_instruction)) + ? ((0xfe000U & + (vlTOPp->in_instruction + >> 0xcU)) + | (((IData)(vlTOPp->out_rs2) + << 8U) | + (((IData)(vlTOPp->out_rs1) + << 3U) + | (7U & + (vlTOPp->in_instruction + >> 0xcU))))) + : 0U)); + vlTOPp->VX_decode__DOT__jalr_immed = ((0xfe0U & + (vlTOPp->in_instruction + >> 0x14U)) + | (IData)(vlTOPp->out_rs2)); + vlTOPp->VX_decode__DOT__alu_tempp = (0xfffU & ( + ((1U + == + (7U + & (vlTOPp->in_instruction + >> 0xcU))) + | (5U + == + (7U + & (vlTOPp->in_instruction + >> 0xcU)))) + ? (IData)(vlTOPp->out_rs2) + : + (vlTOPp->in_instruction + >> 0x14U))); + // ALWAYS at VX_decode.v:247 + vlTOPp->out_jal_offset = ((0x6fU == (0x7fU & vlTOPp->in_instruction)) + ? ((0xffe00000U & (VL_NEGATE_I((IData)( + (1U + & (vlTOPp->in_instruction + >> 0x1fU)))) + << 0x15U)) + | ((0x100000U & (vlTOPp->in_instruction + >> 0xbU)) + | ((0xff000U & vlTOPp->in_instruction) + | ((0x800U + & (vlTOPp->in_instruction + >> 9U)) + | (0x7feU + & (vlTOPp->in_instruction + >> 0x14U)))))) + : ((0x67U == (0x7fU + & vlTOPp->in_instruction)) + ? ((0xfffff000U + & (VL_NEGATE_I((IData)( + (1U + & ((IData)(vlTOPp->VX_decode__DOT__jalr_immed) + >> 0xbU)))) + << 0xcU)) + | (IData)(vlTOPp->VX_decode__DOT__jalr_immed)) + : ((0x73U == (0x7fU + & vlTOPp->in_instruction)) + ? (((0U == (7U + & (vlTOPp->in_instruction + >> 0xcU))) + & (2U > + (0xfffU + & (vlTOPp->in_instruction + >> 0x14U)))) + ? 0xb0000000U + : 0xdeadbeefU) + : 0xdeadbeefU))); + // ALWAYS at VX_decode.v:295 + vlTOPp->out_itype_immed = ((0x40U & vlTOPp->in_instruction) + ? ((0x20U & vlTOPp->in_instruction) + ? ((0x10U & vlTOPp->in_instruction) + ? 0xdeadbeefU + : ((8U & vlTOPp->in_instruction) + ? 0xdeadbeefU + : ((4U + & vlTOPp->in_instruction) + ? 0xdeadbeefU + : ( + (2U + & vlTOPp->in_instruction) + ? + ((1U + & vlTOPp->in_instruction) + ? + ((0xfffff000U + & (VL_NEGATE_I((IData)( + (1U + & (vlTOPp->in_instruction + >> 0x1fU)))) + << 0xcU)) + | ((0x800U + & (vlTOPp->in_instruction + >> 0x14U)) + | ((0x400U + & (vlTOPp->in_instruction + << 3U)) + | ((0x3f0U + & (vlTOPp->in_instruction + >> 0x15U)) + | (0xfU + & (vlTOPp->in_instruction + >> 8U)))))) + : 0xdeadbeefU) + : 0xdeadbeefU)))) + : 0xdeadbeefU) : + ((0x20U & vlTOPp->in_instruction) + ? ((0x10U & vlTOPp->in_instruction) + ? 0xdeadbeefU : + ((8U & vlTOPp->in_instruction) + ? 0xdeadbeefU + : ((4U & vlTOPp->in_instruction) + ? 0xdeadbeefU + : ((2U & vlTOPp->in_instruction) + ? ((1U + & vlTOPp->in_instruction) + ? + ((0xfffff000U + & (VL_NEGATE_I((IData)( + (1U + & (vlTOPp->in_instruction + >> 0x1fU)))) + << 0xcU)) + | ((0xfe0U + & (vlTOPp->in_instruction + >> 0x14U)) + | (IData)(vlTOPp->out_rd))) + : 0xdeadbeefU) + : 0xdeadbeefU)))) + : ((0x10U & vlTOPp->in_instruction) + ? ((8U & vlTOPp->in_instruction) + ? 0xdeadbeefU + : ((4U & vlTOPp->in_instruction) + ? 0xdeadbeefU + : ((2U + & vlTOPp->in_instruction) + ? + ((1U + & vlTOPp->in_instruction) + ? + ((0xfffff000U + & (VL_NEGATE_I((IData)( + (1U + & ((IData)(vlTOPp->VX_decode__DOT__alu_tempp) + >> 0xbU)))) + << 0xcU)) + | (IData)(vlTOPp->VX_decode__DOT__alu_tempp)) + : 0xdeadbeefU) + : 0xdeadbeefU))) + : ((8U & vlTOPp->in_instruction) + ? 0xdeadbeefU + : ((4U & vlTOPp->in_instruction) + ? 0xdeadbeefU + : ((2U + & vlTOPp->in_instruction) + ? + ((1U + & vlTOPp->in_instruction) + ? + ((0xfffff000U + & (VL_NEGATE_I((IData)( + (1U + & (vlTOPp->in_instruction + >> 0x1fU)))) + << 0xcU)) + | (0xfffU + & (vlTOPp->in_instruction + >> 0x14U))) + : 0xdeadbeefU) + : 0xdeadbeefU)))))); +} + +void VVX_decode::_settle__TOP__2(VVX_decode__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_decode::_settle__TOP__2\n"); ); + VVX_decode* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->out_PC_next = ((IData)(4U) + vlTOPp->in_curr_PC); + vlTOPp->out_mem_read = (7U & ((3U == (0x7fU & vlTOPp->in_instruction)) + ? (vlTOPp->in_instruction + >> 0xcU) : 7U)); + vlTOPp->out_mem_write = (7U & ((0x23U == (0x7fU + & vlTOPp->in_instruction)) + ? (vlTOPp->in_instruction + >> 0xcU) : 7U)); + // ALWAYS at VX_decode.v:247 + vlTOPp->out_jal = ((0x6fU == (0x7fU & vlTOPp->in_instruction)) + | ((0x67U == (0x7fU & vlTOPp->in_instruction)) + | ((0x73U == (0x7fU & vlTOPp->in_instruction)) + & ((0U == (7U & (vlTOPp->in_instruction + >> 0xcU))) + & (2U > (0xfffU & (vlTOPp->in_instruction + >> 0x14U))))))); + vlTOPp->out_csr_address = (0xfffU & (((0U != (7U + & (vlTOPp->in_instruction + >> 0xcU))) + & (2U <= + (0xfffU + & (vlTOPp->in_instruction + >> 0x14U)))) + ? (vlTOPp->in_instruction + >> 0x14U) + : 0x55U)); + // ALWAYS at VX_decode.v:306 + vlTOPp->out_branch_stall = ((0x63U == (0x7fU & vlTOPp->in_instruction)) + | ((0x6fU == (0x7fU + & vlTOPp->in_instruction)) + | (0x67U == (0x7fU + & vlTOPp->in_instruction)))); + vlTOPp->out_rd = (0x1fU & (vlTOPp->in_instruction + >> 7U)); + // ALWAYS at VX_decode.v:306 + vlTOPp->out_branch_type = ((0x63U == (0x7fU & vlTOPp->in_instruction)) + ? ((0x4000U & vlTOPp->in_instruction) + ? ((0x2000U & vlTOPp->in_instruction) + ? ((0x1000U + & vlTOPp->in_instruction) + ? 6U : 5U) + : ((0x1000U + & vlTOPp->in_instruction) + ? 4U : 3U)) + : ((0x2000U & vlTOPp->in_instruction) + ? 0U : ((0x1000U + & vlTOPp->in_instruction) + ? 2U + : 1U))) + : 0U); + vlTOPp->VX_decode__DOT__is_itype = ((0x13U == (0x7fU + & vlTOPp->in_instruction)) + | (3U == (0x7fU + & vlTOPp->in_instruction))); + vlTOPp->VX_decode__DOT__is_csr = ((0x73U == (0x7fU + & vlTOPp->in_instruction)) + & (0U != (7U + & (vlTOPp->in_instruction + >> 0xcU)))); + vlTOPp->out_rs1 = (0x1fU & (vlTOPp->in_instruction + >> 0xfU)); + vlTOPp->out_rs2 = (0x1fU & (vlTOPp->in_instruction + >> 0x14U)); + vlTOPp->out_rs2_src = (1U & (((IData)(vlTOPp->VX_decode__DOT__is_itype) + | (0x23U == (0x7fU + & vlTOPp->in_instruction))) + ? 1U : 0U)); + vlTOPp->out_is_csr = vlTOPp->VX_decode__DOT__is_csr; + vlTOPp->out_wb = ((((0x6fU == (0x7fU & vlTOPp->in_instruction)) + | (0x67U == (0x7fU & vlTOPp->in_instruction))) + | ((0x73U == (0x7fU & vlTOPp->in_instruction)) + & (0U == (7U & (vlTOPp->in_instruction + >> 0xcU))))) + ? 3U : ((3U == (0x7fU & vlTOPp->in_instruction)) + ? 2U : ((((((IData)(vlTOPp->VX_decode__DOT__is_itype) + | (0x33U + == (0x7fU + & vlTOPp->in_instruction))) + | (0x37U + == (0x7fU + & vlTOPp->in_instruction))) + | (0x17U + == (0x7fU + & vlTOPp->in_instruction))) + | (IData)(vlTOPp->VX_decode__DOT__is_csr)) + ? 1U : 0U))); + vlTOPp->out_alu_op = ((0x63U == (0x7fU & vlTOPp->in_instruction)) + ? ((5U > (IData)(vlTOPp->out_branch_type)) + ? 1U : 0xaU) : ((0x37U + == + (0x7fU + & vlTOPp->in_instruction)) + ? 0xbU + : ( + (0x17U + == + (0x7fU + & vlTOPp->in_instruction)) + ? 0xcU + : + ((IData)(vlTOPp->VX_decode__DOT__is_csr) + ? + ((1U + == + (3U + & (vlTOPp->in_instruction + >> 0xcU))) + ? 0xdU + : + ((2U + == + (3U + & (vlTOPp->in_instruction + >> 0xcU))) + ? 0xeU + : 0xfU)) + : + (((0x23U + == + (0x7fU + & vlTOPp->in_instruction)) + | (3U + == + (0x7fU + & vlTOPp->in_instruction))) + ? 0U + : + ((0x4000U + & vlTOPp->in_instruction) + ? + ((0x2000U + & vlTOPp->in_instruction) + ? + ((0x1000U + & vlTOPp->in_instruction) + ? 9U + : 8U) + : + ((0x1000U + & vlTOPp->in_instruction) + ? + ((0U + == + (0x7fU + & (vlTOPp->in_instruction + >> 0x19U))) + ? 6U + : 7U) + : 5U)) + : + ((0x2000U + & vlTOPp->in_instruction) + ? + ((0x1000U + & vlTOPp->in_instruction) + ? 4U + : 3U) + : + ((0x1000U + & vlTOPp->in_instruction) + ? 2U + : + ((0x13U + == + (0x7fU + & vlTOPp->in_instruction)) + ? 0U + : + ((0U + == + (0x7fU + & (vlTOPp->in_instruction + >> 0x19U))) + ? 0U + : 1U)))))))))); + vlTOPp->out_rd1 = ((0x6fU == (0x7fU & vlTOPp->in_instruction)) + ? vlTOPp->in_curr_PC : ((IData)(vlTOPp->in_src1_fwd) + ? vlTOPp->in_src1_fwd_data + : + vlTOPp->VX_decode__DOT__vx_register_file__DOT__registers + [vlTOPp->out_rs1])); + // ALWAYS at VX_decode.v:201 + vlTOPp->out_upper_immed = ((0x37U == (0x7fU & vlTOPp->in_instruction)) + ? ((0xfe000U & (vlTOPp->in_instruction + >> 0xcU)) + | (((IData)(vlTOPp->out_rs2) + << 8U) | (((IData)(vlTOPp->out_rs1) + << 3U) + | (7U + & (vlTOPp->in_instruction + >> 0xcU))))) + : ((0x17U == (0x7fU + & vlTOPp->in_instruction)) + ? ((0xfe000U & + (vlTOPp->in_instruction + >> 0xcU)) + | (((IData)(vlTOPp->out_rs2) + << 8U) | + (((IData)(vlTOPp->out_rs1) + << 3U) + | (7U & + (vlTOPp->in_instruction + >> 0xcU))))) + : 0U)); + vlTOPp->VX_decode__DOT__jalr_immed = ((0xfe0U & + (vlTOPp->in_instruction + >> 0x14U)) + | (IData)(vlTOPp->out_rs2)); + vlTOPp->VX_decode__DOT__alu_tempp = (0xfffU & ( + ((1U + == + (7U + & (vlTOPp->in_instruction + >> 0xcU))) + | (5U + == + (7U + & (vlTOPp->in_instruction + >> 0xcU)))) + ? (IData)(vlTOPp->out_rs2) + : + (vlTOPp->in_instruction + >> 0x14U))); + vlTOPp->out_rd2 = ((IData)(vlTOPp->in_src2_fwd) + ? vlTOPp->in_src2_fwd_data : + vlTOPp->VX_decode__DOT__vx_register_file__DOT__registers + [vlTOPp->out_rs2]); + vlTOPp->out_csr_mask = (((IData)(vlTOPp->VX_decode__DOT__is_csr) + & (vlTOPp->in_instruction + >> 0xeU)) ? (IData)(vlTOPp->out_rs1) + : vlTOPp->out_rd1); + // ALWAYS at VX_decode.v:247 + vlTOPp->out_jal_offset = ((0x6fU == (0x7fU & vlTOPp->in_instruction)) + ? ((0xffe00000U & (VL_NEGATE_I((IData)( + (1U + & (vlTOPp->in_instruction + >> 0x1fU)))) + << 0x15U)) + | ((0x100000U & (vlTOPp->in_instruction + >> 0xbU)) + | ((0xff000U & vlTOPp->in_instruction) + | ((0x800U + & (vlTOPp->in_instruction + >> 9U)) + | (0x7feU + & (vlTOPp->in_instruction + >> 0x14U)))))) + : ((0x67U == (0x7fU + & vlTOPp->in_instruction)) + ? ((0xfffff000U + & (VL_NEGATE_I((IData)( + (1U + & ((IData)(vlTOPp->VX_decode__DOT__jalr_immed) + >> 0xbU)))) + << 0xcU)) + | (IData)(vlTOPp->VX_decode__DOT__jalr_immed)) + : ((0x73U == (0x7fU + & vlTOPp->in_instruction)) + ? (((0U == (7U + & (vlTOPp->in_instruction + >> 0xcU))) + & (2U > + (0xfffU + & (vlTOPp->in_instruction + >> 0x14U)))) + ? 0xb0000000U + : 0xdeadbeefU) + : 0xdeadbeefU))); + // ALWAYS at VX_decode.v:295 + vlTOPp->out_itype_immed = ((0x40U & vlTOPp->in_instruction) + ? ((0x20U & vlTOPp->in_instruction) + ? ((0x10U & vlTOPp->in_instruction) + ? 0xdeadbeefU + : ((8U & vlTOPp->in_instruction) + ? 0xdeadbeefU + : ((4U + & vlTOPp->in_instruction) + ? 0xdeadbeefU + : ( + (2U + & vlTOPp->in_instruction) + ? + ((1U + & vlTOPp->in_instruction) + ? + ((0xfffff000U + & (VL_NEGATE_I((IData)( + (1U + & (vlTOPp->in_instruction + >> 0x1fU)))) + << 0xcU)) + | ((0x800U + & (vlTOPp->in_instruction + >> 0x14U)) + | ((0x400U + & (vlTOPp->in_instruction + << 3U)) + | ((0x3f0U + & (vlTOPp->in_instruction + >> 0x15U)) + | (0xfU + & (vlTOPp->in_instruction + >> 8U)))))) + : 0xdeadbeefU) + : 0xdeadbeefU)))) + : 0xdeadbeefU) : + ((0x20U & vlTOPp->in_instruction) + ? ((0x10U & vlTOPp->in_instruction) + ? 0xdeadbeefU : + ((8U & vlTOPp->in_instruction) + ? 0xdeadbeefU + : ((4U & vlTOPp->in_instruction) + ? 0xdeadbeefU + : ((2U & vlTOPp->in_instruction) + ? ((1U + & vlTOPp->in_instruction) + ? + ((0xfffff000U + & (VL_NEGATE_I((IData)( + (1U + & (vlTOPp->in_instruction + >> 0x1fU)))) + << 0xcU)) + | ((0xfe0U + & (vlTOPp->in_instruction + >> 0x14U)) + | (IData)(vlTOPp->out_rd))) + : 0xdeadbeefU) + : 0xdeadbeefU)))) + : ((0x10U & vlTOPp->in_instruction) + ? ((8U & vlTOPp->in_instruction) + ? 0xdeadbeefU + : ((4U & vlTOPp->in_instruction) + ? 0xdeadbeefU + : ((2U + & vlTOPp->in_instruction) + ? + ((1U + & vlTOPp->in_instruction) + ? + ((0xfffff000U + & (VL_NEGATE_I((IData)( + (1U + & ((IData)(vlTOPp->VX_decode__DOT__alu_tempp) + >> 0xbU)))) + << 0xcU)) + | (IData)(vlTOPp->VX_decode__DOT__alu_tempp)) + : 0xdeadbeefU) + : 0xdeadbeefU))) + : ((8U & vlTOPp->in_instruction) + ? 0xdeadbeefU + : ((4U & vlTOPp->in_instruction) + ? 0xdeadbeefU + : ((2U + & vlTOPp->in_instruction) + ? + ((1U + & vlTOPp->in_instruction) + ? + ((0xfffff000U + & (VL_NEGATE_I((IData)( + (1U + & (vlTOPp->in_instruction + >> 0x1fU)))) + << 0xcU)) + | (0xfffU + & (vlTOPp->in_instruction + >> 0x14U))) + : 0xdeadbeefU) + : 0xdeadbeefU)))))); +} + +VL_INLINE_OPT void VVX_decode::_sequent__TOP__3(VVX_decode__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_decode::_sequent__TOP__3\n"); ); + VVX_decode* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Variables + // Begin mtask footprint all: + VL_SIG8(__Vdlyvdim0__VX_decode__DOT__vx_register_file__DOT__registers__v0,4,0); + VL_SIG8(__Vdlyvset__VX_decode__DOT__vx_register_file__DOT__registers__v0,0,0); + VL_SIG(__Vdlyvval__VX_decode__DOT__vx_register_file__DOT__registers__v0,31,0); + // Body + __Vdlyvset__VX_decode__DOT__vx_register_file__DOT__registers__v0 = 0U; + // ALWAYS at VX_register_file.v:30 + if (((0U != (IData)(vlTOPp->in_wb)) & (0U != (IData)(vlTOPp->in_rd)))) { + __Vdlyvval__VX_decode__DOT__vx_register_file__DOT__registers__v0 + = vlTOPp->in_write_data; + __Vdlyvset__VX_decode__DOT__vx_register_file__DOT__registers__v0 = 1U; + __Vdlyvdim0__VX_decode__DOT__vx_register_file__DOT__registers__v0 + = vlTOPp->in_rd; + } + // ALWAYSPOST at VX_register_file.v:32 + if (__Vdlyvset__VX_decode__DOT__vx_register_file__DOT__registers__v0) { + vlTOPp->VX_decode__DOT__vx_register_file__DOT__registers[__Vdlyvdim0__VX_decode__DOT__vx_register_file__DOT__registers__v0] + = __Vdlyvval__VX_decode__DOT__vx_register_file__DOT__registers__v0; + } +} + +VL_INLINE_OPT void VVX_decode::_combo__TOP__4(VVX_decode__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_decode::_combo__TOP__4\n"); ); + VVX_decode* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->out_rd2 = ((IData)(vlTOPp->in_src2_fwd) + ? vlTOPp->in_src2_fwd_data : + vlTOPp->VX_decode__DOT__vx_register_file__DOT__registers + [vlTOPp->out_rs2]); + vlTOPp->out_rd1 = ((0x6fU == (0x7fU & vlTOPp->in_instruction)) + ? vlTOPp->in_curr_PC : ((IData)(vlTOPp->in_src1_fwd) + ? vlTOPp->in_src1_fwd_data + : + vlTOPp->VX_decode__DOT__vx_register_file__DOT__registers + [vlTOPp->out_rs1])); + vlTOPp->out_csr_mask = (((IData)(vlTOPp->VX_decode__DOT__is_csr) + & (vlTOPp->in_instruction + >> 0xeU)) ? (IData)(vlTOPp->out_rs1) + : vlTOPp->out_rd1); +} + +void VVX_decode::_eval(VVX_decode__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_decode::_eval\n"); ); + VVX_decode* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->_combo__TOP__1(vlSymsp); + if (((IData)(vlTOPp->clk) & (~ (IData)(vlTOPp->__Vclklast__TOP__clk)))) { + vlTOPp->_sequent__TOP__3(vlSymsp); + } + vlTOPp->_combo__TOP__4(vlSymsp); + // Final + vlTOPp->__Vclklast__TOP__clk = vlTOPp->clk; +} + +void VVX_decode::_eval_initial(VVX_decode__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_decode::_eval_initial\n"); ); + VVX_decode* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->__Vclklast__TOP__clk = vlTOPp->clk; +} + +void VVX_decode::final() { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_decode::final\n"); ); + // Variables + VVX_decode__Syms* __restrict vlSymsp = this->__VlSymsp; + VVX_decode* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; +} + +void VVX_decode::_eval_settle(VVX_decode__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_decode::_eval_settle\n"); ); + VVX_decode* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->_settle__TOP__2(vlSymsp); +} + +VL_INLINE_OPT QData VVX_decode::_change_request(VVX_decode__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_decode::_change_request\n"); ); + VVX_decode* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + // Change detection + QData __req = false; // Logically a bool + return __req; +} + +#ifdef VL_DEBUG +void VVX_decode::_eval_debug_assertions() { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_decode::_eval_debug_assertions\n"); ); + // Body + if (VL_UNLIKELY((clk & 0xfeU))) { + Verilated::overWidthError("clk");} + if (VL_UNLIKELY((in_rd & 0xe0U))) { + Verilated::overWidthError("in_rd");} + if (VL_UNLIKELY((in_wb & 0xfcU))) { + Verilated::overWidthError("in_wb");} + if (VL_UNLIKELY((in_src1_fwd & 0xfeU))) { + Verilated::overWidthError("in_src1_fwd");} + if (VL_UNLIKELY((in_src2_fwd & 0xfeU))) { + Verilated::overWidthError("in_src2_fwd");} +} +#endif // VL_DEBUG + +void VVX_decode::_ctor_var_reset() { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_decode::_ctor_var_reset\n"); ); + // Body + clk = VL_RAND_RESET_I(1); + in_instruction = VL_RAND_RESET_I(32); + in_curr_PC = VL_RAND_RESET_I(32); + in_write_data = VL_RAND_RESET_I(32); + in_rd = VL_RAND_RESET_I(5); + in_wb = VL_RAND_RESET_I(2); + in_src1_fwd = VL_RAND_RESET_I(1); + in_src1_fwd_data = VL_RAND_RESET_I(32); + in_src2_fwd = VL_RAND_RESET_I(1); + in_src2_fwd_data = VL_RAND_RESET_I(32); + out_csr_address = VL_RAND_RESET_I(12); + out_is_csr = VL_RAND_RESET_I(1); + out_csr_mask = VL_RAND_RESET_I(32); + out_rd = VL_RAND_RESET_I(5); + out_rs1 = VL_RAND_RESET_I(5); + out_rd1 = VL_RAND_RESET_I(32); + out_rs2 = VL_RAND_RESET_I(5); + out_rd2 = VL_RAND_RESET_I(32); + out_wb = VL_RAND_RESET_I(2); + out_alu_op = VL_RAND_RESET_I(4); + out_rs2_src = VL_RAND_RESET_I(1); + out_itype_immed = VL_RAND_RESET_I(32); + out_mem_read = VL_RAND_RESET_I(3); + out_mem_write = VL_RAND_RESET_I(3); + out_branch_type = VL_RAND_RESET_I(3); + out_branch_stall = VL_RAND_RESET_I(1); + out_jal = VL_RAND_RESET_I(1); + out_jal_offset = VL_RAND_RESET_I(32); + out_upper_immed = VL_RAND_RESET_I(20); + out_PC_next = VL_RAND_RESET_I(32); + VX_decode__DOT__is_itype = VL_RAND_RESET_I(1); + VX_decode__DOT__is_csr = VL_RAND_RESET_I(1); + VX_decode__DOT__jalr_immed = VL_RAND_RESET_I(12); + VX_decode__DOT__alu_tempp = VL_RAND_RESET_I(12); + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + VX_decode__DOT__vx_register_file__DOT__registers[__Vi0] = VL_RAND_RESET_I(32); + }} +} diff --git a/rtl/obj_dir/VVX_decode.h b/rtl/obj_dir/VVX_decode.h new file mode 100644 index 00000000..b439480b --- /dev/null +++ b/rtl/obj_dir/VVX_decode.h @@ -0,0 +1,118 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Primary design header +// +// This header should be included by all source files instantiating the design. +// The class here is then constructed to instantiate the design. +// See the Verilator manual for examples. + +#ifndef _VVX_decode_H_ +#define _VVX_decode_H_ + +#include "verilated.h" + +class VVX_decode__Syms; + +//---------- + +VL_MODULE(VVX_decode) { + public: + + // PORTS + // The application code writes and reads these signals to + // propagate new values into/out from the Verilated model. + // Begin mtask footprint all: + VL_IN8(clk,0,0); + VL_IN8(in_rd,4,0); + VL_IN8(in_wb,1,0); + VL_IN8(in_src1_fwd,0,0); + VL_IN8(in_src2_fwd,0,0); + VL_OUT8(out_is_csr,0,0); + VL_OUT8(out_rd,4,0); + VL_OUT8(out_rs1,4,0); + VL_OUT8(out_rs2,4,0); + VL_OUT8(out_wb,1,0); + VL_OUT8(out_alu_op,3,0); + VL_OUT8(out_rs2_src,0,0); + VL_OUT8(out_mem_read,2,0); + VL_OUT8(out_mem_write,2,0); + VL_OUT8(out_branch_type,2,0); + VL_OUT8(out_branch_stall,0,0); + VL_OUT8(out_jal,0,0); + VL_OUT16(out_csr_address,11,0); + VL_IN(in_instruction,31,0); + VL_IN(in_curr_PC,31,0); + VL_IN(in_write_data,31,0); + VL_IN(in_src1_fwd_data,31,0); + VL_IN(in_src2_fwd_data,31,0); + VL_OUT(out_csr_mask,31,0); + VL_OUT(out_rd1,31,0); + VL_OUT(out_rd2,31,0); + VL_OUT(out_itype_immed,31,0); + VL_OUT(out_jal_offset,31,0); + VL_OUT(out_upper_immed,19,0); + VL_OUT(out_PC_next,31,0); + + // LOCAL SIGNALS + // Internals; generally not touched by application code + // Begin mtask footprint all: + VL_SIG8(VX_decode__DOT__is_itype,0,0); + VL_SIG8(VX_decode__DOT__is_csr,0,0); + VL_SIG16(VX_decode__DOT__jalr_immed,11,0); + VL_SIG16(VX_decode__DOT__alu_tempp,11,0); + VL_SIG(VX_decode__DOT__vx_register_file__DOT__registers[32],31,0); + + // LOCAL VARIABLES + // Internals; generally not touched by application code + // Begin mtask footprint all: + VL_SIG8(__Vclklast__TOP__clk,0,0); + + // INTERNAL VARIABLES + // Internals; generally not touched by application code + VVX_decode__Syms* __VlSymsp; // Symbol table + + // PARAMETERS + // Parameters marked /*verilator public*/ for use by application code + + // CONSTRUCTORS + private: + VL_UNCOPYABLE(VVX_decode); ///< Copying not allowed + public: + /// Construct the model; called by application code + /// The special name may be used to make a wrapper with a + /// single model invisible with respect to DPI scope names. + VVX_decode(const char* name="TOP"); + /// Destroy the model; called (often implicitly) by application code + ~VVX_decode(); + + // API METHODS + /// Evaluate the model. Application must call when inputs change. + void eval(); + /// Simulation complete, run final blocks. Application must call on completion. + void final(); + + // INTERNAL METHODS + private: + static void _eval_initial_loop(VVX_decode__Syms* __restrict vlSymsp); + public: + void __Vconfigure(VVX_decode__Syms* symsp, bool first); + private: + static QData _change_request(VVX_decode__Syms* __restrict vlSymsp); + public: + static void _combo__TOP__1(VVX_decode__Syms* __restrict vlSymsp); + static void _combo__TOP__4(VVX_decode__Syms* __restrict vlSymsp); + private: + void _ctor_var_reset(); + public: + static void _eval(VVX_decode__Syms* __restrict vlSymsp); + private: +#ifdef VL_DEBUG + void _eval_debug_assertions(); +#endif // VL_DEBUG + public: + static void _eval_initial(VVX_decode__Syms* __restrict vlSymsp); + static void _eval_settle(VVX_decode__Syms* __restrict vlSymsp); + static void _sequent__TOP__3(VVX_decode__Syms* __restrict vlSymsp); + static void _settle__TOP__2(VVX_decode__Syms* __restrict vlSymsp); +} VL_ATTR_ALIGNED(128); + +#endif // guard diff --git a/rtl/obj_dir/VVX_decode.mk b/rtl/obj_dir/VVX_decode.mk new file mode 100644 index 00000000..2cf73106 --- /dev/null +++ b/rtl/obj_dir/VVX_decode.mk @@ -0,0 +1,53 @@ +# Verilated -*- Makefile -*- +# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable +# +# Execute this makefile from the object directory: +# make -f VVX_decode.mk + +default: VVX_decode__ALL.a + +### Constants... +# Perl executable (from $PERL) +PERL = perl +# Path to Verilator kit (from $VERILATOR_ROOT) +VERILATOR_ROOT = /usr/local/Cellar/verilator/4.010/share/verilator +# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE) +SYSTEMC_INCLUDE ?= +# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR) +SYSTEMC_LIBDIR ?= + +### Switches... +# SystemC output mode? 0/1 (from --sc) +VM_SC = 0 +# Legacy or SystemC output mode? 0/1 (from --sc) +VM_SP_OR_SC = $(VM_SC) +# Deprecated +VM_PCLI = 1 +# Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH) +VM_SC_TARGET_ARCH = linux + +### Vars... +# Design prefix (from --prefix) +VM_PREFIX = VVX_decode +# Module prefix (from --prefix) +VM_MODPREFIX = VVX_decode +# User CFLAGS (from -CFLAGS on Verilator command line) +VM_USER_CFLAGS = \ + +# User LDLIBS (from -LDFLAGS on Verilator command line) +VM_USER_LDLIBS = \ + +# User .cpp files (from .cpp's on Verilator command line) +VM_USER_CLASSES = \ + +# User .cpp directories (from .cpp's on Verilator command line) +VM_USER_DIR = \ + + +### Default rules... +# Include list of all generated classes +include VVX_decode_classes.mk +# Include global rules +include $(VERILATOR_ROOT)/include/verilated.mk + +# Verilated -*- Makefile -*- diff --git a/rtl/obj_dir/VVX_decode__Syms.cpp b/rtl/obj_dir/VVX_decode__Syms.cpp new file mode 100644 index 00000000..e53318ee --- /dev/null +++ b/rtl/obj_dir/VVX_decode__Syms.cpp @@ -0,0 +1,19 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Symbol table implementation internals + +#include "VVX_decode__Syms.h" +#include "VVX_decode.h" + +// FUNCTIONS +VVX_decode__Syms::VVX_decode__Syms(VVX_decode* topp, const char* namep) + // Setup locals + : __Vm_namep(namep) + , __Vm_didInit(false) + // Setup submodule names +{ + // Pointer to top level + TOPp = topp; + // Setup each module's pointers to their submodules + // Setup each module's pointer back to symbol table (for public functions) + TOPp->__Vconfigure(this, true); +} diff --git a/rtl/obj_dir/VVX_decode__Syms.h b/rtl/obj_dir/VVX_decode__Syms.h new file mode 100644 index 00000000..cc253e91 --- /dev/null +++ b/rtl/obj_dir/VVX_decode__Syms.h @@ -0,0 +1,34 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Symbol table internal header +// +// Internal details; most calling programs do not need this header + +#ifndef _VVX_decode__Syms_H_ +#define _VVX_decode__Syms_H_ + +#include "verilated.h" + +// INCLUDE MODULE CLASSES +#include "VVX_decode.h" + +// SYMS CLASS +class VVX_decode__Syms : public VerilatedSyms { + public: + + // LOCAL STATE + const char* __Vm_namep; + bool __Vm_didInit; + + // SUBCELL STATE + VVX_decode* TOPp; + + // CREATORS + VVX_decode__Syms(VVX_decode* topp, const char* namep); + ~VVX_decode__Syms() {} + + // METHODS + inline const char* name() { return __Vm_namep; } + +} VL_ATTR_ALIGNED(64); + +#endif // guard diff --git a/rtl/obj_dir/VVX_decode__ver.d b/rtl/obj_dir/VVX_decode__ver.d new file mode 100644 index 00000000..74c6bceb --- /dev/null +++ b/rtl/obj_dir/VVX_decode__ver.d @@ -0,0 +1 @@ +obj_dir/VVX_decode.cpp obj_dir/VVX_decode.h obj_dir/VVX_decode.mk obj_dir/VVX_decode__Syms.cpp obj_dir/VVX_decode__Syms.h obj_dir/VVX_decode__ver.d obj_dir/VVX_decode_classes.mk : /usr/local/Cellar/verilator/4.010/bin/verilator_bin /usr/local/Cellar/verilator/4.010/bin/verilator_bin VX_decode.v VX_register_file.v diff --git a/rtl/obj_dir/VVX_decode__verFiles.dat b/rtl/obj_dir/VVX_decode__verFiles.dat new file mode 100644 index 00000000..ebf887f0 --- /dev/null +++ b/rtl/obj_dir/VVX_decode__verFiles.dat @@ -0,0 +1,13 @@ +# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will. +C "-Wall -cc VX_decode.v VX_register_file.v" +S 4608404 12889046060 1553037052 0 1548678579 0 "/usr/local/Cellar/verilator/4.010/bin/verilator_bin" +S 9277 12889063385 1553149232 0 1553149232 0 "VX_decode.v" +S 726 12889070228 1553138880 0 1553138880 0 "VX_register_file.v" +T 30372 12889070221 1553149234 0 1553149234 0 "obj_dir/VVX_decode.cpp" +T 3820 12889070220 1553149234 0 1553149234 0 "obj_dir/VVX_decode.h" +T 1476 12889070223 1553149234 0 1553149234 0 "obj_dir/VVX_decode.mk" +T 545 12889070219 1553149234 0 1553149234 0 "obj_dir/VVX_decode__Syms.cpp" +T 732 12889070218 1553149234 0 1553149234 0 "obj_dir/VVX_decode__Syms.h" +T 319 12889070301 1553149234 0 1553149234 0 "obj_dir/VVX_decode__ver.d" +T 0 0 1553149234 0 1553149234 0 "obj_dir/VVX_decode__verFiles.dat" +T 1168 12889070222 1553149234 0 1553149234 0 "obj_dir/VVX_decode_classes.mk" diff --git a/rtl/obj_dir/VVX_decode_classes.mk b/rtl/obj_dir/VVX_decode_classes.mk new file mode 100644 index 00000000..d4f4e2bf --- /dev/null +++ b/rtl/obj_dir/VVX_decode_classes.mk @@ -0,0 +1,38 @@ +# Verilated -*- Makefile -*- +# DESCRIPTION: Verilator output: Make include file with class lists +# +# This file lists generated Verilated files, for including in higher level makefiles. +# See VVX_decode.mk for the caller. + +### Switches... +# Coverage output mode? 0/1 (from --coverage) +VM_COVERAGE = 0 +# Threaded output mode? 0/1/N threads (from --threads) +VM_THREADS = 0 +# Tracing output mode? 0/1 (from --trace) +VM_TRACE = 0 + +### Object file lists... +# Generated module classes, fast-path, compile with highest optimization +VM_CLASSES_FAST += \ + VVX_decode \ + +# Generated module classes, non-fast-path, compile with low/medium optimization +VM_CLASSES_SLOW += \ + +# Generated support classes, fast-path, compile with highest optimization +VM_SUPPORT_FAST += \ + +# Generated support classes, non-fast-path, compile with low/medium optimization +VM_SUPPORT_SLOW += \ + VVX_decode__Syms \ + +# Global classes, need linked once per executable, fast-path, compile with highest optimization +VM_GLOBAL_FAST += \ + verilated \ + +# Global classes, need linked once per executable, non-fast-path, compile with low/medium optimization +VM_GLOBAL_SLOW += \ + + +# Verilated -*- Makefile -*- diff --git a/rtl/obj_dir/VVX_register_file.cpp b/rtl/obj_dir/VVX_register_file.cpp new file mode 100644 index 00000000..917863e8 --- /dev/null +++ b/rtl/obj_dir/VVX_register_file.cpp @@ -0,0 +1,200 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Design implementation internals +// See VVX_register_file.h for the primary calling header + +#include "VVX_register_file.h" +#include "VVX_register_file__Syms.h" + + +//-------------------- +// STATIC VARIABLES + + +//-------------------- + +VL_CTOR_IMP(VVX_register_file) { + VVX_register_file__Syms* __restrict vlSymsp = __VlSymsp = new VVX_register_file__Syms(this, name()); + VVX_register_file* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Reset internal values + + // Reset structure values + _ctor_var_reset(); +} + +void VVX_register_file::__Vconfigure(VVX_register_file__Syms* vlSymsp, bool first) { + if (0 && first) {} // Prevent unused + this->__VlSymsp = vlSymsp; +} + +VVX_register_file::~VVX_register_file() { + delete __VlSymsp; __VlSymsp=NULL; +} + +//-------------------- + + +void VVX_register_file::eval() { + VL_DEBUG_IF(VL_DBG_MSGF("+++++TOP Evaluate VVX_register_file::eval\n"); ); + VVX_register_file__Syms* __restrict vlSymsp = this->__VlSymsp; // Setup global symbol table + VVX_register_file* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; +#ifdef VL_DEBUG + // Debug assertions + _eval_debug_assertions(); +#endif // VL_DEBUG + // Initialize + if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) _eval_initial_loop(vlSymsp); + // Evaluate till stable + int __VclockLoop = 0; + QData __Vchange = 1; + do { + VL_DEBUG_IF(VL_DBG_MSGF("+ Clock loop\n");); + _eval(vlSymsp); + if (VL_UNLIKELY(++__VclockLoop > 100)) { + // About to fail, so enable debug to see what's not settling. + // Note you must run make with OPT=-DVL_DEBUG for debug prints. + int __Vsaved_debug = Verilated::debug(); + Verilated::debug(1); + __Vchange = _change_request(vlSymsp); + Verilated::debug(__Vsaved_debug); + VL_FATAL_MT(__FILE__,__LINE__,__FILE__,"Verilated model didn't converge"); + } else { + __Vchange = _change_request(vlSymsp); + } + } while (VL_UNLIKELY(__Vchange)); +} + +void VVX_register_file::_eval_initial_loop(VVX_register_file__Syms* __restrict vlSymsp) { + vlSymsp->__Vm_didInit = true; + _eval_initial(vlSymsp); + // Evaluate till stable + int __VclockLoop = 0; + QData __Vchange = 1; + do { + _eval_settle(vlSymsp); + _eval(vlSymsp); + if (VL_UNLIKELY(++__VclockLoop > 100)) { + // About to fail, so enable debug to see what's not settling. + // Note you must run make with OPT=-DVL_DEBUG for debug prints. + int __Vsaved_debug = Verilated::debug(); + Verilated::debug(1); + __Vchange = _change_request(vlSymsp); + Verilated::debug(__Vsaved_debug); + VL_FATAL_MT(__FILE__,__LINE__,__FILE__,"Verilated model didn't DC converge"); + } else { + __Vchange = _change_request(vlSymsp); + } + } while (VL_UNLIKELY(__Vchange)); +} + +//-------------------- +// Internal Methods + +VL_INLINE_OPT void VVX_register_file::_sequent__TOP__1(VVX_register_file__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_register_file::_sequent__TOP__1\n"); ); + VVX_register_file* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Variables + // Begin mtask footprint all: + VL_SIG8(__Vdlyvdim0__VX_register_file__DOT__registers__v0,4,0); + VL_SIG8(__Vdlyvset__VX_register_file__DOT__registers__v0,0,0); + VL_SIG(__Vdlyvval__VX_register_file__DOT__registers__v0,31,0); + // Body + __Vdlyvset__VX_register_file__DOT__registers__v0 = 0U; + // ALWAYS at VX_register_file.v:30 + if (((IData)(vlTOPp->in_write_register) & (0U != (IData)(vlTOPp->in_rd)))) { + __Vdlyvval__VX_register_file__DOT__registers__v0 + = vlTOPp->in_data; + __Vdlyvset__VX_register_file__DOT__registers__v0 = 1U; + __Vdlyvdim0__VX_register_file__DOT__registers__v0 + = vlTOPp->in_rd; + } + // ALWAYSPOST at VX_register_file.v:32 + if (__Vdlyvset__VX_register_file__DOT__registers__v0) { + vlTOPp->VX_register_file__DOT__registers[__Vdlyvdim0__VX_register_file__DOT__registers__v0] + = __Vdlyvval__VX_register_file__DOT__registers__v0; + } +} + +VL_INLINE_OPT void VVX_register_file::_settle__TOP__2(VVX_register_file__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_register_file::_settle__TOP__2\n"); ); + VVX_register_file* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->out_src1_data = vlTOPp->VX_register_file__DOT__registers + [vlTOPp->in_src1]; + vlTOPp->out_src2_data = vlTOPp->VX_register_file__DOT__registers + [vlTOPp->in_src2]; +} + +void VVX_register_file::_eval(VVX_register_file__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_register_file::_eval\n"); ); + VVX_register_file* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + if (((IData)(vlTOPp->clk) & (~ (IData)(vlTOPp->__Vclklast__TOP__clk)))) { + vlTOPp->_sequent__TOP__1(vlSymsp); + } + vlTOPp->_settle__TOP__2(vlSymsp); + // Final + vlTOPp->__Vclklast__TOP__clk = vlTOPp->clk; +} + +void VVX_register_file::_eval_initial(VVX_register_file__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_register_file::_eval_initial\n"); ); + VVX_register_file* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->__Vclklast__TOP__clk = vlTOPp->clk; +} + +void VVX_register_file::final() { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_register_file::final\n"); ); + // Variables + VVX_register_file__Syms* __restrict vlSymsp = this->__VlSymsp; + VVX_register_file* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; +} + +void VVX_register_file::_eval_settle(VVX_register_file__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_register_file::_eval_settle\n"); ); + VVX_register_file* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->_settle__TOP__2(vlSymsp); +} + +VL_INLINE_OPT QData VVX_register_file::_change_request(VVX_register_file__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_register_file::_change_request\n"); ); + VVX_register_file* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + // Change detection + QData __req = false; // Logically a bool + return __req; +} + +#ifdef VL_DEBUG +void VVX_register_file::_eval_debug_assertions() { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_register_file::_eval_debug_assertions\n"); ); + // Body + if (VL_UNLIKELY((clk & 0xfeU))) { + Verilated::overWidthError("clk");} + if (VL_UNLIKELY((in_write_register & 0xfeU))) { + Verilated::overWidthError("in_write_register");} + if (VL_UNLIKELY((in_rd & 0xe0U))) { + Verilated::overWidthError("in_rd");} + if (VL_UNLIKELY((in_src1 & 0xe0U))) { + Verilated::overWidthError("in_src1");} + if (VL_UNLIKELY((in_src2 & 0xe0U))) { + Verilated::overWidthError("in_src2");} +} +#endif // VL_DEBUG + +void VVX_register_file::_ctor_var_reset() { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_register_file::_ctor_var_reset\n"); ); + // Body + clk = VL_RAND_RESET_I(1); + in_write_register = VL_RAND_RESET_I(1); + in_rd = VL_RAND_RESET_I(5); + in_data = VL_RAND_RESET_I(32); + in_src1 = VL_RAND_RESET_I(5); + in_src2 = VL_RAND_RESET_I(5); + out_src1_data = VL_RAND_RESET_I(32); + out_src2_data = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + VX_register_file__DOT__registers[__Vi0] = VL_RAND_RESET_I(32); + }} +} diff --git a/rtl/obj_dir/VVX_register_file.h b/rtl/obj_dir/VVX_register_file.h new file mode 100644 index 00000000..4a73c470 --- /dev/null +++ b/rtl/obj_dir/VVX_register_file.h @@ -0,0 +1,88 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Primary design header +// +// This header should be included by all source files instantiating the design. +// The class here is then constructed to instantiate the design. +// See the Verilator manual for examples. + +#ifndef _VVX_register_file_H_ +#define _VVX_register_file_H_ + +#include "verilated.h" + +class VVX_register_file__Syms; + +//---------- + +VL_MODULE(VVX_register_file) { + public: + + // PORTS + // The application code writes and reads these signals to + // propagate new values into/out from the Verilated model. + // Begin mtask footprint all: + VL_IN8(clk,0,0); + VL_IN8(in_write_register,0,0); + VL_IN8(in_rd,4,0); + VL_IN8(in_src1,4,0); + VL_IN8(in_src2,4,0); + VL_IN(in_data,31,0); + VL_OUT(out_src1_data,31,0); + VL_OUT(out_src2_data,31,0); + + // LOCAL SIGNALS + // Internals; generally not touched by application code + // Begin mtask footprint all: + VL_SIG(VX_register_file__DOT__registers[32],31,0); + + // LOCAL VARIABLES + // Internals; generally not touched by application code + // Begin mtask footprint all: + VL_SIG8(__Vclklast__TOP__clk,0,0); + + // INTERNAL VARIABLES + // Internals; generally not touched by application code + VVX_register_file__Syms* __VlSymsp; // Symbol table + + // PARAMETERS + // Parameters marked /*verilator public*/ for use by application code + + // CONSTRUCTORS + private: + VL_UNCOPYABLE(VVX_register_file); ///< Copying not allowed + public: + /// Construct the model; called by application code + /// The special name may be used to make a wrapper with a + /// single model invisible with respect to DPI scope names. + VVX_register_file(const char* name="TOP"); + /// Destroy the model; called (often implicitly) by application code + ~VVX_register_file(); + + // API METHODS + /// Evaluate the model. Application must call when inputs change. + void eval(); + /// Simulation complete, run final blocks. Application must call on completion. + void final(); + + // INTERNAL METHODS + private: + static void _eval_initial_loop(VVX_register_file__Syms* __restrict vlSymsp); + public: + void __Vconfigure(VVX_register_file__Syms* symsp, bool first); + private: + static QData _change_request(VVX_register_file__Syms* __restrict vlSymsp); + void _ctor_var_reset(); + public: + static void _eval(VVX_register_file__Syms* __restrict vlSymsp); + private: +#ifdef VL_DEBUG + void _eval_debug_assertions(); +#endif // VL_DEBUG + public: + static void _eval_initial(VVX_register_file__Syms* __restrict vlSymsp); + static void _eval_settle(VVX_register_file__Syms* __restrict vlSymsp); + static void _sequent__TOP__1(VVX_register_file__Syms* __restrict vlSymsp); + static void _settle__TOP__2(VVX_register_file__Syms* __restrict vlSymsp); +} VL_ATTR_ALIGNED(128); + +#endif // guard diff --git a/rtl/obj_dir/VVX_register_file.mk b/rtl/obj_dir/VVX_register_file.mk new file mode 100644 index 00000000..9582c9dd --- /dev/null +++ b/rtl/obj_dir/VVX_register_file.mk @@ -0,0 +1,53 @@ +# Verilated -*- Makefile -*- +# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable +# +# Execute this makefile from the object directory: +# make -f VVX_register_file.mk + +default: VVX_register_file__ALL.a + +### Constants... +# Perl executable (from $PERL) +PERL = perl +# Path to Verilator kit (from $VERILATOR_ROOT) +VERILATOR_ROOT = /usr/local/Cellar/verilator/4.010/share/verilator +# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE) +SYSTEMC_INCLUDE ?= +# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR) +SYSTEMC_LIBDIR ?= + +### Switches... +# SystemC output mode? 0/1 (from --sc) +VM_SC = 0 +# Legacy or SystemC output mode? 0/1 (from --sc) +VM_SP_OR_SC = $(VM_SC) +# Deprecated +VM_PCLI = 1 +# Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH) +VM_SC_TARGET_ARCH = linux + +### Vars... +# Design prefix (from --prefix) +VM_PREFIX = VVX_register_file +# Module prefix (from --prefix) +VM_MODPREFIX = VVX_register_file +# User CFLAGS (from -CFLAGS on Verilator command line) +VM_USER_CFLAGS = \ + +# User LDLIBS (from -LDFLAGS on Verilator command line) +VM_USER_LDLIBS = \ + +# User .cpp files (from .cpp's on Verilator command line) +VM_USER_CLASSES = \ + +# User .cpp directories (from .cpp's on Verilator command line) +VM_USER_DIR = \ + + +### Default rules... +# Include list of all generated classes +include VVX_register_file_classes.mk +# Include global rules +include $(VERILATOR_ROOT)/include/verilated.mk + +# Verilated -*- Makefile -*- diff --git a/rtl/obj_dir/VVX_register_file__Syms.cpp b/rtl/obj_dir/VVX_register_file__Syms.cpp new file mode 100644 index 00000000..7e308ad4 --- /dev/null +++ b/rtl/obj_dir/VVX_register_file__Syms.cpp @@ -0,0 +1,19 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Symbol table implementation internals + +#include "VVX_register_file__Syms.h" +#include "VVX_register_file.h" + +// FUNCTIONS +VVX_register_file__Syms::VVX_register_file__Syms(VVX_register_file* topp, const char* namep) + // Setup locals + : __Vm_namep(namep) + , __Vm_didInit(false) + // Setup submodule names +{ + // Pointer to top level + TOPp = topp; + // Setup each module's pointers to their submodules + // Setup each module's pointer back to symbol table (for public functions) + TOPp->__Vconfigure(this, true); +} diff --git a/rtl/obj_dir/VVX_register_file__Syms.h b/rtl/obj_dir/VVX_register_file__Syms.h new file mode 100644 index 00000000..5a894634 --- /dev/null +++ b/rtl/obj_dir/VVX_register_file__Syms.h @@ -0,0 +1,34 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Symbol table internal header +// +// Internal details; most calling programs do not need this header + +#ifndef _VVX_register_file__Syms_H_ +#define _VVX_register_file__Syms_H_ + +#include "verilated.h" + +// INCLUDE MODULE CLASSES +#include "VVX_register_file.h" + +// SYMS CLASS +class VVX_register_file__Syms : public VerilatedSyms { + public: + + // LOCAL STATE + const char* __Vm_namep; + bool __Vm_didInit; + + // SUBCELL STATE + VVX_register_file* TOPp; + + // CREATORS + VVX_register_file__Syms(VVX_register_file* topp, const char* namep); + ~VVX_register_file__Syms() {} + + // METHODS + inline const char* name() { return __Vm_namep; } + +} VL_ATTR_ALIGNED(64); + +#endif // guard diff --git a/rtl/obj_dir/VVX_register_file__ver.d b/rtl/obj_dir/VVX_register_file__ver.d new file mode 100644 index 00000000..22986176 --- /dev/null +++ b/rtl/obj_dir/VVX_register_file__ver.d @@ -0,0 +1 @@ +obj_dir/VVX_register_file.cpp obj_dir/VVX_register_file.h obj_dir/VVX_register_file.mk obj_dir/VVX_register_file__Syms.cpp obj_dir/VVX_register_file__Syms.h obj_dir/VVX_register_file__ver.d obj_dir/VVX_register_file_classes.mk : /usr/local/Cellar/verilator/4.010/bin/verilator_bin /usr/local/Cellar/verilator/4.010/bin/verilator_bin VX_register_file.v diff --git a/rtl/obj_dir/VVX_register_file__verFiles.dat b/rtl/obj_dir/VVX_register_file__verFiles.dat new file mode 100644 index 00000000..cf49288e --- /dev/null +++ b/rtl/obj_dir/VVX_register_file__verFiles.dat @@ -0,0 +1,12 @@ +# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will. +C "-Wall -cc VX_register_file.v" +S 4608404 12889046060 1553037052 0 1548678579 0 "/usr/local/Cellar/verilator/4.010/bin/verilator_bin" +S 726 12889070228 1553138880 0 1553138880 0 "VX_register_file.v" +T 7234 12889070262 1553138884 0 1553138884 0 "obj_dir/VVX_register_file.cpp" +T 2914 12889070261 1553138884 0 1553138884 0 "obj_dir/VVX_register_file.h" +T 1511 12889070264 1553138884 0 1553138884 0 "obj_dir/VVX_register_file.mk" +T 580 12889070260 1553138884 0 1553138884 0 "obj_dir/VVX_register_file__Syms.cpp" +T 781 12889070259 1553138884 0 1553138884 0 "obj_dir/VVX_register_file__Syms.h" +T 356 12889070265 1553138884 0 1553138884 0 "obj_dir/VVX_register_file__ver.d" +T 0 0 1553138884 0 1553138884 0 "obj_dir/VVX_register_file__verFiles.dat" +T 1189 12889070263 1553138884 0 1553138884 0 "obj_dir/VVX_register_file_classes.mk" diff --git a/rtl/obj_dir/VVX_register_file_classes.mk b/rtl/obj_dir/VVX_register_file_classes.mk new file mode 100644 index 00000000..b22b228d --- /dev/null +++ b/rtl/obj_dir/VVX_register_file_classes.mk @@ -0,0 +1,38 @@ +# Verilated -*- Makefile -*- +# DESCRIPTION: Verilator output: Make include file with class lists +# +# This file lists generated Verilated files, for including in higher level makefiles. +# See VVX_register_file.mk for the caller. + +### Switches... +# Coverage output mode? 0/1 (from --coverage) +VM_COVERAGE = 0 +# Threaded output mode? 0/1/N threads (from --threads) +VM_THREADS = 0 +# Tracing output mode? 0/1 (from --trace) +VM_TRACE = 0 + +### Object file lists... +# Generated module classes, fast-path, compile with highest optimization +VM_CLASSES_FAST += \ + VVX_register_file \ + +# Generated module classes, non-fast-path, compile with low/medium optimization +VM_CLASSES_SLOW += \ + +# Generated support classes, fast-path, compile with highest optimization +VM_SUPPORT_FAST += \ + +# Generated support classes, non-fast-path, compile with low/medium optimization +VM_SUPPORT_SLOW += \ + VVX_register_file__Syms \ + +# Global classes, need linked once per executable, fast-path, compile with highest optimization +VM_GLOBAL_FAST += \ + verilated \ + +# Global classes, need linked once per executable, non-fast-path, compile with low/medium optimization +VM_GLOBAL_SLOW += \ + + +# Verilated -*- Makefile -*- diff --git a/rtl/obj_dir/Vvortex b/rtl/obj_dir/Vvortex new file mode 100755 index 00000000..ddd33aa9 Binary files /dev/null and b/rtl/obj_dir/Vvortex differ diff --git a/rtl/obj_dir/Vvortex.cpp b/rtl/obj_dir/Vvortex.cpp new file mode 100644 index 00000000..75abd27f --- /dev/null +++ b/rtl/obj_dir/Vvortex.cpp @@ -0,0 +1,304 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Design implementation internals +// See Vvortex.h for the primary calling header + +#include "Vvortex.h" +#include "Vvortex__Syms.h" + + +//-------------------- +// STATIC VARIABLES + + +//-------------------- + +VL_CTOR_IMP(Vvortex) { + Vvortex__Syms* __restrict vlSymsp = __VlSymsp = new Vvortex__Syms(this, name()); + Vvortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Reset internal values + + // Reset structure values + _ctor_var_reset(); +} + +void Vvortex::__Vconfigure(Vvortex__Syms* vlSymsp, bool first) { + if (0 && first) {} // Prevent unused + this->__VlSymsp = vlSymsp; +} + +Vvortex::~Vvortex() { + delete __VlSymsp; __VlSymsp=NULL; +} + +//-------------------- + + +void Vvortex::eval() { + VL_DEBUG_IF(VL_DBG_MSGF("+++++TOP Evaluate Vvortex::eval\n"); ); + Vvortex__Syms* __restrict vlSymsp = this->__VlSymsp; // Setup global symbol table + Vvortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; +#ifdef VL_DEBUG + // Debug assertions + _eval_debug_assertions(); +#endif // VL_DEBUG + // Initialize + if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) _eval_initial_loop(vlSymsp); + // Evaluate till stable + int __VclockLoop = 0; + QData __Vchange = 1; + do { + VL_DEBUG_IF(VL_DBG_MSGF("+ Clock loop\n");); + _eval(vlSymsp); + if (VL_UNLIKELY(++__VclockLoop > 100)) { + // About to fail, so enable debug to see what's not settling. + // Note you must run make with OPT=-DVL_DEBUG for debug prints. + int __Vsaved_debug = Verilated::debug(); + Verilated::debug(1); + __Vchange = _change_request(vlSymsp); + Verilated::debug(__Vsaved_debug); + VL_FATAL_MT(__FILE__,__LINE__,__FILE__,"Verilated model didn't converge"); + } else { + __Vchange = _change_request(vlSymsp); + } + } while (VL_UNLIKELY(__Vchange)); +} + +void Vvortex::_eval_initial_loop(Vvortex__Syms* __restrict vlSymsp) { + vlSymsp->__Vm_didInit = true; + _eval_initial(vlSymsp); + // Evaluate till stable + int __VclockLoop = 0; + QData __Vchange = 1; + do { + _eval_settle(vlSymsp); + _eval(vlSymsp); + if (VL_UNLIKELY(++__VclockLoop > 100)) { + // About to fail, so enable debug to see what's not settling. + // Note you must run make with OPT=-DVL_DEBUG for debug prints. + int __Vsaved_debug = Verilated::debug(); + Verilated::debug(1); + __Vchange = _change_request(vlSymsp); + Verilated::debug(__Vsaved_debug); + VL_FATAL_MT(__FILE__,__LINE__,__FILE__,"Verilated model didn't DC converge"); + } else { + __Vchange = _change_request(vlSymsp); + } + } while (VL_UNLIKELY(__Vchange)); +} + +//-------------------- +// Internal Methods + +void Vvortex::_settle__TOP__1(Vvortex__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vvortex::_settle__TOP__1\n"); ); + Vvortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->fe_delay = 0U; + vlTOPp->de_instruction = vlTOPp->vortex__DOT__vx_f_d_reg__DOT__instruction; +} + +VL_INLINE_OPT void Vvortex::_sequent__TOP__2(Vvortex__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vvortex::_sequent__TOP__2\n"); ); + Vvortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + // ALWAYS at VX_fetch.v:128 + vlTOPp->vortex__DOT__vx_fetch__DOT__delay_reg = 0U; + // ALWAYS at VX_fetch.v:128 + vlTOPp->vortex__DOT__vx_fetch__DOT__stall_reg = 0U; + // ALWAYS at VX_fetch.v:128 + vlTOPp->vortex__DOT__vx_fetch__DOT__JAL_reg = ((IData)(vlTOPp->reset) + ? 0U + : 4U); + // ALWAYS at VX_fetch.v:128 + vlTOPp->vortex__DOT__vx_fetch__DOT__BR_reg = ((IData)(vlTOPp->reset) + ? 0U + : 4U); + // ALWAYS at VX_fetch.v:128 + vlTOPp->vortex__DOT__vx_fetch__DOT__real_PC = ((IData)(vlTOPp->reset) + ? 0U + : + ((IData)(4U) + + vlTOPp->vortex__DOT__vx_fetch__DOT__PC_to_use)); + // ALWAYS at VX_fetch.v:128 + vlTOPp->vortex__DOT__vx_fetch__DOT__old = ((IData)(vlTOPp->reset) + ? 0U + : vlTOPp->vortex__DOT__vx_fetch__DOT__PC_to_use); + // ALWAYS at VX_fetch.v:128 + vlTOPp->vortex__DOT__vx_fetch__DOT__state = ((IData)(vlTOPp->reset) + ? 0U + : + ((IData)(vlTOPp->vortex__DOT__vx_fetch__DOT__prev_debug) + ? 4U + : 0U)); + // ALWAYS at VX_fetch.v:128 + vlTOPp->vortex__DOT__vx_fetch__DOT__prev_debug = 0U; + // ALWAYS at VX_fetch.v:71 + vlTOPp->vortex__DOT__vx_fetch__DOT__PC_to_use = + ((IData)(vlTOPp->vortex__DOT__vx_fetch__DOT__delay_reg) + ? vlTOPp->vortex__DOT__vx_fetch__DOT__old + : ((IData)(vlTOPp->vortex__DOT__vx_fetch__DOT__stall_reg) + ? vlTOPp->vortex__DOT__vx_fetch__DOT__old + : ((0x10U & (IData)(vlTOPp->vortex__DOT__vx_fetch__DOT__state)) + ? 0U : ((8U & (IData)(vlTOPp->vortex__DOT__vx_fetch__DOT__state)) + ? 0U : ((4U & (IData)(vlTOPp->vortex__DOT__vx_fetch__DOT__state)) + ? ((2U & (IData)(vlTOPp->vortex__DOT__vx_fetch__DOT__state)) + ? 0U : ((1U + & (IData)(vlTOPp->vortex__DOT__vx_fetch__DOT__state)) + ? 0U + : vlTOPp->vortex__DOT__vx_fetch__DOT__old)) + : ((2U & (IData)(vlTOPp->vortex__DOT__vx_fetch__DOT__state)) + ? ((1U & (IData)(vlTOPp->vortex__DOT__vx_fetch__DOT__state)) + ? vlTOPp->vortex__DOT__vx_fetch__DOT__real_PC + : vlTOPp->vortex__DOT__vx_fetch__DOT__BR_reg) + : ((1U & (IData)(vlTOPp->vortex__DOT__vx_fetch__DOT__state)) + ? vlTOPp->vortex__DOT__vx_fetch__DOT__JAL_reg + : vlTOPp->vortex__DOT__vx_fetch__DOT__real_PC))))))); + vlTOPp->curr_PC = vlTOPp->vortex__DOT__vx_fetch__DOT__PC_to_use; +} + +VL_INLINE_OPT void Vvortex::_sequent__TOP__3(Vvortex__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vvortex::_sequent__TOP__3\n"); ); + Vvortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + // ALWAYS at VX_f_d_reg.v:17 + VL_WRITEF("Fetch Inst: %10#\tDecode Inst: %10#\n", + 32,vlTOPp->fe_instruction,32,vlTOPp->vortex__DOT__vx_f_d_reg__DOT__instruction); +} + +void Vvortex::_initial__TOP__4(Vvortex__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vvortex::_initial__TOP__4\n"); ); + Vvortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + // INITIAL at VX_fetch.v:44 + vlTOPp->vortex__DOT__vx_fetch__DOT__stall_reg = 0U; + vlTOPp->vortex__DOT__vx_fetch__DOT__delay_reg = 0U; + vlTOPp->vortex__DOT__vx_fetch__DOT__old = 0U; + vlTOPp->vortex__DOT__vx_fetch__DOT__state = 0U; + vlTOPp->vortex__DOT__vx_fetch__DOT__real_PC = 0U; + vlTOPp->vortex__DOT__vx_fetch__DOT__JAL_reg = 0U; + vlTOPp->vortex__DOT__vx_fetch__DOT__BR_reg = 0U; + vlTOPp->vortex__DOT__vx_fetch__DOT__prev_debug = 0U; +} + +VL_INLINE_OPT void Vvortex::_sequent__TOP__5(Vvortex__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vvortex::_sequent__TOP__5\n"); ); + Vvortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + // ALWAYS at VX_f_d_reg.v:26 + vlTOPp->vortex__DOT__vx_f_d_reg__DOT__instruction + = ((IData)(vlTOPp->reset) ? 0U : vlTOPp->fe_instruction); + vlTOPp->de_instruction = vlTOPp->vortex__DOT__vx_f_d_reg__DOT__instruction; +} + +void Vvortex::_settle__TOP__6(Vvortex__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vvortex::_settle__TOP__6\n"); ); + Vvortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + // ALWAYS at VX_fetch.v:71 + vlTOPp->vortex__DOT__vx_fetch__DOT__PC_to_use = + ((IData)(vlTOPp->vortex__DOT__vx_fetch__DOT__delay_reg) + ? vlTOPp->vortex__DOT__vx_fetch__DOT__old + : ((IData)(vlTOPp->vortex__DOT__vx_fetch__DOT__stall_reg) + ? vlTOPp->vortex__DOT__vx_fetch__DOT__old + : ((0x10U & (IData)(vlTOPp->vortex__DOT__vx_fetch__DOT__state)) + ? 0U : ((8U & (IData)(vlTOPp->vortex__DOT__vx_fetch__DOT__state)) + ? 0U : ((4U & (IData)(vlTOPp->vortex__DOT__vx_fetch__DOT__state)) + ? ((2U & (IData)(vlTOPp->vortex__DOT__vx_fetch__DOT__state)) + ? 0U : ((1U + & (IData)(vlTOPp->vortex__DOT__vx_fetch__DOT__state)) + ? 0U + : vlTOPp->vortex__DOT__vx_fetch__DOT__old)) + : ((2U & (IData)(vlTOPp->vortex__DOT__vx_fetch__DOT__state)) + ? ((1U & (IData)(vlTOPp->vortex__DOT__vx_fetch__DOT__state)) + ? vlTOPp->vortex__DOT__vx_fetch__DOT__real_PC + : vlTOPp->vortex__DOT__vx_fetch__DOT__BR_reg) + : ((1U & (IData)(vlTOPp->vortex__DOT__vx_fetch__DOT__state)) + ? vlTOPp->vortex__DOT__vx_fetch__DOT__JAL_reg + : vlTOPp->vortex__DOT__vx_fetch__DOT__real_PC))))))); + vlTOPp->curr_PC = vlTOPp->vortex__DOT__vx_fetch__DOT__PC_to_use; +} + +void Vvortex::_eval(Vvortex__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vvortex::_eval\n"); ); + Vvortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + if ((((IData)(vlTOPp->clk) & (~ (IData)(vlTOPp->__Vclklast__TOP__clk))) + | ((IData)(vlTOPp->reset) & (~ (IData)(vlTOPp->__Vclklast__TOP__reset))))) { + vlTOPp->_sequent__TOP__2(vlSymsp); + } + if (((IData)(vlTOPp->clk) & (~ (IData)(vlTOPp->__Vclklast__TOP__clk)))) { + vlTOPp->_sequent__TOP__3(vlSymsp); + } + if ((((IData)(vlTOPp->clk) & (~ (IData)(vlTOPp->__Vclklast__TOP__clk))) + | ((IData)(vlTOPp->reset) & (~ (IData)(vlTOPp->__Vclklast__TOP__reset))))) { + vlTOPp->_sequent__TOP__5(vlSymsp); + } + // Final + vlTOPp->__Vclklast__TOP__clk = vlTOPp->clk; + vlTOPp->__Vclklast__TOP__reset = vlTOPp->reset; +} + +void Vvortex::_eval_initial(Vvortex__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vvortex::_eval_initial\n"); ); + Vvortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->__Vclklast__TOP__clk = vlTOPp->clk; + vlTOPp->__Vclklast__TOP__reset = vlTOPp->reset; + vlTOPp->_initial__TOP__4(vlSymsp); +} + +void Vvortex::final() { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vvortex::final\n"); ); + // Variables + Vvortex__Syms* __restrict vlSymsp = this->__VlSymsp; + Vvortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; +} + +void Vvortex::_eval_settle(Vvortex__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vvortex::_eval_settle\n"); ); + Vvortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->_settle__TOP__1(vlSymsp); + vlTOPp->_settle__TOP__6(vlSymsp); +} + +VL_INLINE_OPT QData Vvortex::_change_request(Vvortex__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vvortex::_change_request\n"); ); + Vvortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + // Change detection + QData __req = false; // Logically a bool + return __req; +} + +#ifdef VL_DEBUG +void Vvortex::_eval_debug_assertions() { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vvortex::_eval_debug_assertions\n"); ); + // Body + if (VL_UNLIKELY((clk & 0xfeU))) { + Verilated::overWidthError("clk");} + if (VL_UNLIKELY((reset & 0xfeU))) { + Verilated::overWidthError("reset");} +} +#endif // VL_DEBUG + +void Vvortex::_ctor_var_reset() { + VL_DEBUG_IF(VL_DBG_MSGF("+ Vvortex::_ctor_var_reset\n"); ); + // Body + clk = VL_RAND_RESET_I(1); + reset = VL_RAND_RESET_I(1); + fe_instruction = VL_RAND_RESET_I(32); + curr_PC = VL_RAND_RESET_I(32); + de_instruction = VL_RAND_RESET_I(32); + fe_delay = VL_RAND_RESET_I(1); + vortex__DOT__vx_fetch__DOT__stall_reg = VL_RAND_RESET_I(1); + vortex__DOT__vx_fetch__DOT__delay_reg = VL_RAND_RESET_I(1); + vortex__DOT__vx_fetch__DOT__old = VL_RAND_RESET_I(32); + vortex__DOT__vx_fetch__DOT__state = VL_RAND_RESET_I(5); + vortex__DOT__vx_fetch__DOT__real_PC = VL_RAND_RESET_I(32); + vortex__DOT__vx_fetch__DOT__JAL_reg = VL_RAND_RESET_I(32); + vortex__DOT__vx_fetch__DOT__BR_reg = VL_RAND_RESET_I(32); + vortex__DOT__vx_fetch__DOT__prev_debug = VL_RAND_RESET_I(1); + vortex__DOT__vx_fetch__DOT__PC_to_use = VL_RAND_RESET_I(32); + vortex__DOT__vx_f_d_reg__DOT__instruction = VL_RAND_RESET_I(32); +} diff --git a/rtl/obj_dir/Vvortex.h b/rtl/obj_dir/Vvortex.h new file mode 100644 index 00000000..543ae44c --- /dev/null +++ b/rtl/obj_dir/Vvortex.h @@ -0,0 +1,100 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Primary design header +// +// This header should be included by all source files instantiating the design. +// The class here is then constructed to instantiate the design. +// See the Verilator manual for examples. + +#ifndef _Vvortex_H_ +#define _Vvortex_H_ + +#include "verilated_heavy.h" + +class Vvortex__Syms; + +//---------- + +VL_MODULE(Vvortex) { + public: + + // PORTS + // The application code writes and reads these signals to + // propagate new values into/out from the Verilated model. + // Begin mtask footprint all: + VL_IN8(clk,0,0); + VL_IN8(reset,0,0); + VL_OUT8(fe_delay,0,0); + VL_IN(fe_instruction,31,0); + VL_OUT(curr_PC,31,0); + VL_OUT(de_instruction,31,0); + + // LOCAL SIGNALS + // Internals; generally not touched by application code + // Begin mtask footprint all: + VL_SIG8(vortex__DOT__vx_fetch__DOT__stall_reg,0,0); + VL_SIG8(vortex__DOT__vx_fetch__DOT__delay_reg,0,0); + VL_SIG8(vortex__DOT__vx_fetch__DOT__state,4,0); + VL_SIG8(vortex__DOT__vx_fetch__DOT__prev_debug,0,0); + VL_SIG(vortex__DOT__vx_fetch__DOT__old,31,0); + VL_SIG(vortex__DOT__vx_fetch__DOT__real_PC,31,0); + VL_SIG(vortex__DOT__vx_fetch__DOT__JAL_reg,31,0); + VL_SIG(vortex__DOT__vx_fetch__DOT__BR_reg,31,0); + VL_SIG(vortex__DOT__vx_fetch__DOT__PC_to_use,31,0); + VL_SIG(vortex__DOT__vx_f_d_reg__DOT__instruction,31,0); + + // LOCAL VARIABLES + // Internals; generally not touched by application code + // Begin mtask footprint all: + VL_SIG8(__Vclklast__TOP__clk,0,0); + VL_SIG8(__Vclklast__TOP__reset,0,0); + + // INTERNAL VARIABLES + // Internals; generally not touched by application code + Vvortex__Syms* __VlSymsp; // Symbol table + + // PARAMETERS + // Parameters marked /*verilator public*/ for use by application code + + // CONSTRUCTORS + private: + VL_UNCOPYABLE(Vvortex); ///< Copying not allowed + public: + /// Construct the model; called by application code + /// The special name may be used to make a wrapper with a + /// single model invisible with respect to DPI scope names. + Vvortex(const char* name="TOP"); + /// Destroy the model; called (often implicitly) by application code + ~Vvortex(); + + // API METHODS + /// Evaluate the model. Application must call when inputs change. + void eval(); + /// Simulation complete, run final blocks. Application must call on completion. + void final(); + + // INTERNAL METHODS + private: + static void _eval_initial_loop(Vvortex__Syms* __restrict vlSymsp); + public: + void __Vconfigure(Vvortex__Syms* symsp, bool first); + private: + static QData _change_request(Vvortex__Syms* __restrict vlSymsp); + void _ctor_var_reset(); + public: + static void _eval(Vvortex__Syms* __restrict vlSymsp); + private: +#ifdef VL_DEBUG + void _eval_debug_assertions(); +#endif // VL_DEBUG + public: + static void _eval_initial(Vvortex__Syms* __restrict vlSymsp); + static void _eval_settle(Vvortex__Syms* __restrict vlSymsp); + static void _initial__TOP__4(Vvortex__Syms* __restrict vlSymsp); + static void _sequent__TOP__2(Vvortex__Syms* __restrict vlSymsp); + static void _sequent__TOP__3(Vvortex__Syms* __restrict vlSymsp); + static void _sequent__TOP__5(Vvortex__Syms* __restrict vlSymsp); + static void _settle__TOP__1(Vvortex__Syms* __restrict vlSymsp); + static void _settle__TOP__6(Vvortex__Syms* __restrict vlSymsp); +} VL_ATTR_ALIGNED(128); + +#endif // guard diff --git a/rtl/obj_dir/Vvortex.mk b/rtl/obj_dir/Vvortex.mk new file mode 100644 index 00000000..16ce24fa --- /dev/null +++ b/rtl/obj_dir/Vvortex.mk @@ -0,0 +1,66 @@ +# Verilated -*- Makefile -*- +# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable +# +# Execute this makefile from the object directory: +# make -f Vvortex.mk + +default: Vvortex + +### Constants... +# Perl executable (from $PERL) +PERL = perl +# Path to Verilator kit (from $VERILATOR_ROOT) +VERILATOR_ROOT = /usr/local/Cellar/verilator/4.010/share/verilator +# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE) +SYSTEMC_INCLUDE ?= +# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR) +SYSTEMC_LIBDIR ?= + +### Switches... +# SystemC output mode? 0/1 (from --sc) +VM_SC = 0 +# Legacy or SystemC output mode? 0/1 (from --sc) +VM_SP_OR_SC = $(VM_SC) +# Deprecated +VM_PCLI = 1 +# Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH) +VM_SC_TARGET_ARCH = linux + +### Vars... +# Design prefix (from --prefix) +VM_PREFIX = Vvortex +# Module prefix (from --prefix) +VM_MODPREFIX = Vvortex +# User CFLAGS (from -CFLAGS on Verilator command line) +VM_USER_CFLAGS = \ + +# User LDLIBS (from -LDFLAGS on Verilator command line) +VM_USER_LDLIBS = \ + +# User .cpp files (from .cpp's on Verilator command line) +VM_USER_CLASSES = \ + test_bench \ + +# User .cpp directories (from .cpp's on Verilator command line) +VM_USER_DIR = \ + . \ + + +### Default rules... +# Include list of all generated classes +include Vvortex_classes.mk +# Include global rules +include $(VERILATOR_ROOT)/include/verilated.mk + +### Executable rules... (from --exe) +VPATH += $(VM_USER_DIR) + +test_bench.o: test_bench.cpp + $(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $< + +### Link rules... (from --exe) +Vvortex: $(VK_USER_OBJS) $(VK_GLOBAL_OBJS) $(VM_PREFIX)__ALL.a + $(LINK) $(LDFLAGS) $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) $(SC_LIBS) + + +# Verilated -*- Makefile -*- diff --git a/rtl/obj_dir/Vvortex__ALL.a b/rtl/obj_dir/Vvortex__ALL.a new file mode 100644 index 00000000..b01d2b92 Binary files /dev/null and b/rtl/obj_dir/Vvortex__ALL.a differ diff --git a/rtl/obj_dir/Vvortex__ALLcls.cpp b/rtl/obj_dir/Vvortex__ALLcls.cpp new file mode 100644 index 00000000..e5902852 --- /dev/null +++ b/rtl/obj_dir/Vvortex__ALLcls.cpp @@ -0,0 +1,3 @@ +// DESCRIPTION: Generated by verilator_includer via makefile +#define VL_INCLUDE_OPT include +#include "Vvortex.cpp" diff --git a/rtl/obj_dir/Vvortex__ALLcls.d b/rtl/obj_dir/Vvortex__ALLcls.d new file mode 100644 index 00000000..31e5a639 --- /dev/null +++ b/rtl/obj_dir/Vvortex__ALLcls.d @@ -0,0 +1,5 @@ +Vvortex__ALLcls.o: Vvortex__ALLcls.cpp Vvortex.cpp Vvortex.h \ + /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_heavy.h \ + /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.h \ + /usr/local/Cellar/verilator/4.010/share/verilator/include/verilatedos.h \ + Vvortex__Syms.h diff --git a/rtl/obj_dir/Vvortex__ALLsup.cpp b/rtl/obj_dir/Vvortex__ALLsup.cpp new file mode 100644 index 00000000..0ec3080d --- /dev/null +++ b/rtl/obj_dir/Vvortex__ALLsup.cpp @@ -0,0 +1,3 @@ +// DESCRIPTION: Generated by verilator_includer via makefile +#define VL_INCLUDE_OPT include +#include "Vvortex__Syms.cpp" diff --git a/rtl/obj_dir/Vvortex__ALLsup.d b/rtl/obj_dir/Vvortex__ALLsup.d new file mode 100644 index 00000000..4864e08b --- /dev/null +++ b/rtl/obj_dir/Vvortex__ALLsup.d @@ -0,0 +1,5 @@ +Vvortex__ALLsup.o: Vvortex__ALLsup.cpp Vvortex__Syms.cpp Vvortex__Syms.h \ + /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_heavy.h \ + /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.h \ + /usr/local/Cellar/verilator/4.010/share/verilator/include/verilatedos.h \ + Vvortex.h diff --git a/rtl/obj_dir/Vvortex__Syms.cpp b/rtl/obj_dir/Vvortex__Syms.cpp new file mode 100644 index 00000000..3d28ef93 --- /dev/null +++ b/rtl/obj_dir/Vvortex__Syms.cpp @@ -0,0 +1,19 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Symbol table implementation internals + +#include "Vvortex__Syms.h" +#include "Vvortex.h" + +// FUNCTIONS +Vvortex__Syms::Vvortex__Syms(Vvortex* topp, const char* namep) + // Setup locals + : __Vm_namep(namep) + , __Vm_didInit(false) + // Setup submodule names +{ + // Pointer to top level + TOPp = topp; + // Setup each module's pointers to their submodules + // Setup each module's pointer back to symbol table (for public functions) + TOPp->__Vconfigure(this, true); +} diff --git a/rtl/obj_dir/Vvortex__Syms.h b/rtl/obj_dir/Vvortex__Syms.h new file mode 100644 index 00000000..c1a5b28d --- /dev/null +++ b/rtl/obj_dir/Vvortex__Syms.h @@ -0,0 +1,34 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Symbol table internal header +// +// Internal details; most calling programs do not need this header + +#ifndef _Vvortex__Syms_H_ +#define _Vvortex__Syms_H_ + +#include "verilated_heavy.h" + +// INCLUDE MODULE CLASSES +#include "Vvortex.h" + +// SYMS CLASS +class Vvortex__Syms : public VerilatedSyms { + public: + + // LOCAL STATE + const char* __Vm_namep; + bool __Vm_didInit; + + // SUBCELL STATE + Vvortex* TOPp; + + // CREATORS + Vvortex__Syms(Vvortex* topp, const char* namep); + ~Vvortex__Syms() {} + + // METHODS + inline const char* name() { return __Vm_namep; } + +} VL_ATTR_ALIGNED(64); + +#endif // guard diff --git a/rtl/obj_dir/Vvortex__ver.d b/rtl/obj_dir/Vvortex__ver.d new file mode 100644 index 00000000..ac6d3fa0 --- /dev/null +++ b/rtl/obj_dir/Vvortex__ver.d @@ -0,0 +1 @@ +obj_dir/Vvortex.cpp obj_dir/Vvortex.h obj_dir/Vvortex.mk obj_dir/Vvortex__Syms.cpp obj_dir/Vvortex__Syms.h obj_dir/Vvortex__ver.d obj_dir/Vvortex_classes.mk : /usr/local/Cellar/verilator/4.010/bin/verilator_bin /usr/local/Cellar/verilator/4.010/bin/verilator_bin VX_f_d_reg.v VX_fetch.v vortex.v diff --git a/rtl/obj_dir/Vvortex__verFiles.dat b/rtl/obj_dir/Vvortex__verFiles.dat new file mode 100644 index 00000000..e19d07f5 --- /dev/null +++ b/rtl/obj_dir/Vvortex__verFiles.dat @@ -0,0 +1,14 @@ +# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will. +C "-Wall -cc vortex.v VX_f_d_reg.v VX_fetch.v --exe test_bench.cpp" +S 4608404 12889046060 1553037052 0 1548678579 0 "/usr/local/Cellar/verilator/4.010/bin/verilator_bin" +S 960 12889050060 1553112201 0 1553112201 0 "VX_f_d_reg.v" +S 3337 12889047675 1553112414 0 1553112414 0 "VX_fetch.v" +T 11853 12889064939 1553112478 0 1553112478 0 "obj_dir/Vvortex.cpp" +T 3513 12889064938 1553112478 0 1553112478 0 "obj_dir/Vvortex.h" +T 1800 12889064941 1553112478 0 1553112478 0 "obj_dir/Vvortex.mk" +T 530 12889064937 1553112478 0 1553112478 0 "obj_dir/Vvortex__Syms.cpp" +T 717 12889064936 1553112478 0 1553112478 0 "obj_dir/Vvortex__Syms.h" +T 300 12889064942 1553112478 0 1553112478 0 "obj_dir/Vvortex__ver.d" +T 0 0 1553112478 0 1553112478 0 "obj_dir/Vvortex__verFiles.dat" +T 1159 12889064940 1553112478 0 1553112478 0 "obj_dir/Vvortex_classes.mk" +S 1826 12889050092 1553109861 0 1553109861 0 "vortex.v" diff --git a/rtl/obj_dir/Vvortex_classes.mk b/rtl/obj_dir/Vvortex_classes.mk new file mode 100644 index 00000000..a7635d5c --- /dev/null +++ b/rtl/obj_dir/Vvortex_classes.mk @@ -0,0 +1,38 @@ +# Verilated -*- Makefile -*- +# DESCRIPTION: Verilator output: Make include file with class lists +# +# This file lists generated Verilated files, for including in higher level makefiles. +# See Vvortex.mk for the caller. + +### Switches... +# Coverage output mode? 0/1 (from --coverage) +VM_COVERAGE = 0 +# Threaded output mode? 0/1/N threads (from --threads) +VM_THREADS = 0 +# Tracing output mode? 0/1 (from --trace) +VM_TRACE = 0 + +### Object file lists... +# Generated module classes, fast-path, compile with highest optimization +VM_CLASSES_FAST += \ + Vvortex \ + +# Generated module classes, non-fast-path, compile with low/medium optimization +VM_CLASSES_SLOW += \ + +# Generated support classes, fast-path, compile with highest optimization +VM_SUPPORT_FAST += \ + +# Generated support classes, non-fast-path, compile with low/medium optimization +VM_SUPPORT_SLOW += \ + Vvortex__Syms \ + +# Global classes, need linked once per executable, fast-path, compile with highest optimization +VM_GLOBAL_FAST += \ + verilated \ + +# Global classes, need linked once per executable, non-fast-path, compile with low/medium optimization +VM_GLOBAL_SLOW += \ + + +# Verilated -*- Makefile -*- diff --git a/rtl/obj_dir/test_bench.d b/rtl/obj_dir/test_bench.d new file mode 100644 index 00000000..047c73b6 --- /dev/null +++ b/rtl/obj_dir/test_bench.d @@ -0,0 +1,4 @@ +test_bench.o: ../test_bench.cpp Vvortex.h \ + /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_heavy.h \ + /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.h \ + /usr/local/Cellar/verilator/4.010/share/verilator/include/verilatedos.h diff --git a/rtl/obj_dir/verilated.d b/rtl/obj_dir/verilated.d new file mode 100644 index 00000000..8fb42837 --- /dev/null +++ b/rtl/obj_dir/verilated.d @@ -0,0 +1,9 @@ +verilated.o: \ + /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.cpp \ + /usr/local/Cellar/verilator/4.010/share/verilator/include/verilatedos.h \ + /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_imp.h \ + /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.h \ + /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_heavy.h \ + /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_syms.h \ + /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_sym_props.h \ + /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_config.h diff --git a/rtl/test_bench.cpp b/rtl/test_bench.cpp new file mode 100644 index 00000000..2875cf99 --- /dev/null +++ b/rtl/test_bench.cpp @@ -0,0 +1,42 @@ +#include "Vvortex.h" +#include "verilated.h" + +#include + +unsigned inst_array[10] = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19}; + +int main(int argc, char **argv) +{ + Verilated::commandArgs(argc, argv); + + Vvortex * vortex = new Vvortex; + + vortex->clk = 0; + vortex->reset = 1; + vortex->eval(); + + vortex->reset = 0; + + for (int i = 0; i < 10; i++) + { + + vortex->fe_instruction = inst_array[(vortex->curr_PC) / 4]; + + vortex->clk = 1; + vortex->eval(); + + vortex->clk = 0; + vortex->eval(); + + + } + + + delete vortex; + + return 0; + +} + + + diff --git a/rtl/vortex.v b/rtl/vortex.v new file mode 100644 index 00000000..2d3fd6c3 --- /dev/null +++ b/rtl/vortex.v @@ -0,0 +1,94 @@ + +// `include "vx_fetch.v" +// `include "vx_f_d_reg.v" + +module vortex( + input wire clk, + input wire reset, + input wire[31:0] fe_instruction, + output wire[31:0] curr_PC, + output wire[31:0] de_instruction, + output wire fe_delay + ); + +wire branch_dir; +assign branch_dir = 0; + +wire freeze; +assign freeze = 0; + +wire[31:0] branch_dest; +wire branch_stall; +wire fwd_stall; +wire branch_stall_exe; +wire jal; +wire[31:0] jal_dest; +wire interrupt; +wire debug; + +assign branch_dest = 32'h0; +assign branch_stall = 1'b0; +assign fwd_stall = 1'b0; +assign branch_stall_exe = 1'b0; +assign jal = 1'b0; +assign jal_dest = 32'h0; +assign interrupt = 1'b0; +assign debug = 1'b0; + + +wire[31:0] f_instruction; +wire f_delay; /* verilator lint_off UNUSED */ +wire[31:0] f_curr_pc; +wire f_valid; + +assign curr_PC = f_curr_pc; +assign fe_delay = f_delay; + +VX_fetch vx_fetch ( + .clk(clk), + .reset(reset), + .in_branch_dir(branch_dir), + .in_freeze(freeze), + .in_branch_dest(branch_dest), + .in_branch_stall(branch_stall), + .in_fwd_stall(fwd_stall), + .in_branch_stall_exe(branch_stall_exe), + .in_jal(jal), + .in_jal_dest(jal_dest), + .in_interrupt(interrupt), + .in_debug(debug), + .in_instruction(fe_instruction), + + .out_instruction(f_instruction), + .out_delay(f_delay), + .out_curr_PC(f_curr_pc), + .out_valid(f_valid) +); + + +wire[31:0] d_curr_pc; +wire[31:0] d_instruction; +wire d_valid; + +VX_f_d_reg vx_f_d_reg ( + .clk(clk), + .reset(reset), + .in_instruction(f_instruction), + .in_valid(f_valid), + .in_curr_PC(f_curr_pc), + .in_fwd_stall(fwd_stall), + .in_freeze(freeze), + .out_instruction(d_instruction), + .out_curr_PC(d_curr_pc), + .out_valid(d_valid) + ); + +assign de_instruction = d_instruction; + + +endmodule // Vortex + + + + + diff --git a/src/vortex_software/.DS_Store b/src/vortex_software/.DS_Store index 476708ba..8f25690d 100644 Binary files a/src/vortex_software/.DS_Store and b/src/vortex_software/.DS_Store differ diff --git a/src/vortex_software/vx_include/.DS_Store b/src/vortex_software/vx_include/.DS_Store new file mode 100644 index 00000000..f03454ae Binary files /dev/null and b/src/vortex_software/vx_include/.DS_Store differ diff --git a/src/vortex_software/vx_os/.DS_Store b/src/vortex_software/vx_os/.DS_Store index 1a403cc6..b0526ab1 100644 Binary files a/src/vortex_software/vx_os/.DS_Store and b/src/vortex_software/vx_os/.DS_Store differ