diff --git a/rtl/VX_decode.v b/rtl/VX_decode.v
index 289b05e1..5afb84cb 100644
--- a/rtl/VX_decode.v
+++ b/rtl/VX_decode.v
@@ -101,29 +101,6 @@ module VX_decode(
 		// wire[31:0] internal_rd1;
 		// wire[31:0] internal_rd2;
 
-		// always @(posedge clk) begin
-		// 	$display("Decode: curr_pc: %h", in_curr_PC);
-		// end
-
-		genvar index;
-
-		generate  
-		for (index=0; index < `NT; index=index+1)  
-		  begin: gen_code_label  
-			VX_register_file vx_register_file(
-				.clk(clk),
-				.in_valid(in_wb_valid[index]),
-				.in_write_register(write_register),
-				.in_rd(in_rd),
-				.in_data(in_write_data[index]),
-				.in_src1(out_rs1),
-				.in_src2(out_rs2),
-				.out_src1_data(rd1_register[index]),
-				.out_src2_data(rd2_register[index])
-			);
-		  end  
-		endgenerate  
-
 		// VX_register_file vx_register_file_0(
 		// 	.clk(clk),
 		// 	.in_valid(in_wb_valid[0]),
@@ -152,6 +129,36 @@ module VX_decode(
 		assign out_valid = in_valid;
 
 		assign write_register = (in_wb != 2'h0) ? (1'b1) : (1'b0);
+
+
+
+		always @(posedge clk) begin
+			$display("Decode: curr_pc: %h", in_curr_PC);
+		end
+
+		genvar index;
+
+		generate  
+		for (index=0; index < `NT; index=index+1)  
+		  begin: gen_code_label  
+			VX_register_file vx_register_file(
+				.clk(clk),
+				.in_valid(in_wb_valid[index]),
+				.in_write_register(write_register),
+				.in_rd(in_rd),
+				.in_data(in_write_data[index]),
+				.in_src1(out_rs1),
+				.in_src2(out_rs2),
+				.out_src1_data(rd1_register[index]),
+				.out_src2_data(rd2_register[index])
+			);
+		  end  
+		endgenerate  
+
+
+
+
+
 		assign curr_opcode    = in_instruction[6:0];
 
 
diff --git a/rtl/VX_define.h b/rtl/VX_define.h
index 0ef8d8b6..77287999 100644
--- a/rtl/VX_define.h
+++ b/rtl/VX_define.h
@@ -1,8 +1,8 @@
 
 
-#define NT 2
-#define NT_M1 1
-#define NT_T2_M1 3
+#define NT 1
+#define NT_M1 0
+#define NT_T2_M1 1
 
 #define R_INST 51
 #define L_INST 3
diff --git a/rtl/VX_define.v b/rtl/VX_define.v
index 5bc5b8ce..0960d4a3 100644
--- a/rtl/VX_define.v
+++ b/rtl/VX_define.v
@@ -1,7 +1,7 @@
 
-`define NT 2
-`define NT_M1 1
-`define NT_T2_M1 3
+`define NT 1
+`define NT_M1 0
+`define NT_T2_M1 1
 
 
 `define R_INST 7'd51
diff --git a/rtl/VX_fetch.v b/rtl/VX_fetch.v
index 43a80b44..534c6c2c 100644
--- a/rtl/VX_fetch.v
+++ b/rtl/VX_fetch.v
@@ -52,7 +52,7 @@ module VX_fetch (
 			// for (ini_cur_th = 0; ini_cur_th < `NT; ini_cur_th=ini_cur_th+1)
 			// 	valid[ini_cur_th]   = 1; // Thread 1 active
 			valid[0]   = 1;
-			valid[1]   = 0;
+			// valid[1]   = 0;
 			stall_reg  = 0;
 			delay_reg  = 0;
 			old        = 0;
diff --git a/rtl/VX_register_file.v b/rtl/VX_register_file.v
index d53552ff..288ad751 100644
--- a/rtl/VX_register_file.v
+++ b/rtl/VX_register_file.v
@@ -35,7 +35,7 @@ module VX_register_file (
 
 	always @(posedge clk) begin
 		if(write_enable) begin
-			// $display("Writing %h to %d",write_data, write_register);
+			$display("Writing %h to %d",write_data, write_register);
 			registers[write_register] <= write_data;
 		end
 	end
diff --git a/rtl/VX_writeback.v b/rtl/VX_writeback.v
index 67687da4..eb402c29 100644
--- a/rtl/VX_writeback.v
+++ b/rtl/VX_writeback.v
@@ -3,6 +3,7 @@
 
 
 module VX_writeback (
+		input wire       clk,
 		input wire[31:0] in_alu_result[`NT_M1:0],
 		input wire[31:0] in_mem_result[`NT_M1:0],
 		input wire[4:0]  in_rd,
@@ -17,12 +18,12 @@ module VX_writeback (
 		wire is_jal;
 		wire uses_alu;
 
-		// always @(*) begin
-		// 	if (in_PC_next == 32'h800001f4 || in_PC_next == 32'h800001f0)  begin
+		always @(negedge clk) begin
+			if (in_wb != 0)  begin
 
-		// 		$display("(%h) WB Data: %h, to register: %d",in_PC_next - 4, in_mem_result, in_rd);
-		// 	end
-		// end
+				$display("(%h) WB Data: %h, to register: %d",in_PC_next - 4, in_mem_result[0], in_rd);
+			end
+		end
 
 		wire[31:0] out_pc_data[`NT_M1:0];
 
diff --git a/rtl/Vortex.v b/rtl/Vortex.v
index ccf83282..ed6678f5 100644
--- a/rtl/Vortex.v
+++ b/rtl/Vortex.v
@@ -381,7 +381,7 @@ VX_e_m_reg vx_e_m_reg(
 wire[31:0]  use_rd2[`NT_M1:0];
 
 assign use_rd2[0] = e_m_reg_data[1];
-assign use_rd2[1] = e_m_reg_data[3];
+// assign use_rd2[1] = e_m_reg_data[3];
 
 VX_memory vx_memory(
 		.in_alu_result                (e_m_alu_result),
@@ -441,6 +441,7 @@ VX_m_w_reg vx_m_w_reg(
 
 
 VX_writeback vx_writeback(
+		.clk           (clk),
 		.in_alu_result (m_w_alu_result),
 		.in_mem_result (m_w_mem_result),
 		.in_rd         (m_w_rd),
diff --git a/rtl/obj_dir/VVortex b/rtl/obj_dir/VVortex
index 29d20758..d4d9adef 100755
Binary files a/rtl/obj_dir/VVortex and b/rtl/obj_dir/VVortex differ
diff --git a/rtl/obj_dir/VVortex.cpp b/rtl/obj_dir/VVortex.cpp
index 5d2717a9..a9dc993e 100644
--- a/rtl/obj_dir/VVortex.cpp
+++ b/rtl/obj_dir/VVortex.cpp
@@ -97,12 +97,11 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__1(VVortex__Syms* __restrict vlSymsp)
     // Variables
     // Begin mtask footprint  all: 
     VL_SIG8(__Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v0,0,0);
-    VL_SIG8(__Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v2,0,0);
-    VL_SIG8(__Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v2,0,0);
-    VL_SIG8(__Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v3,0,0);
+    VL_SIG8(__Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v1,0,0);
+    VL_SIG8(__Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v1,0,0);
     // Body
     __Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v0 = 0U;
-    __Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v2 = 0U;
+    __Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v1 = 0U;
     // ALWAYS at VX_fetch.v:144
     vlTOPp->Vortex__DOT__vx_fetch__DOT__old = ((IData)(vlTOPp->reset)
 					        ? 0U
@@ -129,13 +128,10 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__1(VVortex__Syms* __restrict vlSymsp)
 	__Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v0 = 1U;
     } else {
 	if ((1U & (~ (IData)(vlTOPp->Vortex__DOT__forwarding_fwd_stall)))) {
-	    __Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v2 
-		= vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid
-		[1U];
-	    __Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v2 = 1U;
-	    __Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v3 
+	    __Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v1 
 		= vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid
 		[0U];
+	    __Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v1 = 1U;
 	}
     }
     // ALWAYS at VX_fetch.v:144
@@ -160,17 +156,11 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__1(VVortex__Syms* __restrict vlSymsp)
     // ALWAYSPOST at VX_f_d_reg.v:34
     if (__Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v0) {
 	vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid[0U] = 0U;
-	vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid[1U] = 0U;
     }
-    if (__Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v2) {
-	vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid[1U] 
-	    = __Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v2;
+    if (__Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v1) {
 	vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid[0U] 
-	    = __Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v3;
+	    = __Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v1;
     }
-    vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[1U] 
-	= vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid
-	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[0U] 
 	= vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid
 	[0U];
@@ -197,22 +187,13 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__1(VVortex__Syms* __restrict vlSymsp)
 				        : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__state))
 					    ? vlTOPp->Vortex__DOT__vx_fetch__DOT__JAL_reg
 					    : vlTOPp->Vortex__DOT__vx_fetch__DOT__real_PC)))))));
-    vlTOPp->Vortex__DOT__f_d_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid
-	[1U];
     vlTOPp->Vortex__DOT__f_d_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid
 	[0U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid[1U] 
-	= vlTOPp->Vortex__DOT__f_d_valid[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid[0U] 
 	= vlTOPp->Vortex__DOT__f_d_valid[0U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid[1U] 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid
-	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid[0U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid
 	[0U];
-    vlTOPp->Vortex__DOT__decode_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid
-	[1U];
     vlTOPp->Vortex__DOT__decode_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid
 	[0U];
 }
@@ -224,78 +205,51 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
     // Begin mtask footprint  all: 
     VL_SIG8(__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers__v0,4,0);
     VL_SIG8(__Vdlyvset__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers__v0,0,0);
-    VL_SIG8(__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers__v0,4,0);
-    VL_SIG8(__Vdlyvset__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers__v0,0,0);
     VL_SIG8(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v0,0,0);
-    VL_SIG8(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v1,0,0);
     VL_SIG8(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v0,0,0);
-    VL_SIG8(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v1,0,0);
     VL_SIG8(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v0,0,0);
-    VL_SIG8(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v1,0,0);
     VL_SIG8(__Vdlyvset__Vortex__DOT__vx_csr_handler__DOT__csr__v0,0,0);
     VL_SIG16(__Vdlyvdim0__Vortex__DOT__vx_csr_handler__DOT__csr__v0,11,0);
     VL_SIG16(__Vdlyvval__Vortex__DOT__vx_csr_handler__DOT__csr__v0,11,0);
     VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers__v0,31,0);
-    VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers__v0,31,0);
     VL_SIG(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__reg_data__v0,31,0);
     VL_SIG(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__reg_data__v1,31,0);
-    VL_SIG(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__reg_data__v2,31,0);
-    VL_SIG(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__reg_data__v3,31,0);
     VL_SIG(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v0,31,0);
-    VL_SIG(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v1,31,0);
     VL_SIG(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__reg_data__v0,31,0);
     VL_SIG(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__reg_data__v1,31,0);
-    VL_SIG(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__reg_data__v2,31,0);
-    VL_SIG(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__reg_data__v3,31,0);
-    VL_SIG(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v0,31,0);
-    VL_SIG(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v1,31,0);
     VL_SIG(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v0,31,0);
-    VL_SIG(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v1,31,0);
+    VL_SIG(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v0,31,0);
     // Body
-    __Vdlyvset__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers__v0 = 0U;
     __Vdlyvset__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers__v0 = 0U;
     __Vdlyvset__Vortex__DOT__vx_csr_handler__DOT__csr__v0 = 0U;
+    // ALWAYS at VX_decode.v:135
+    VL_WRITEF("Decode: curr_pc: %x\n",32,vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC);
     // ALWAYS at VX_m_w_reg.v:60
     __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v0 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid
-	[1U];
-    __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v1 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid
 	[0U];
     // ALWAYS at VX_e_m_reg.v:123
     __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v0 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid
-	[1U];
-    __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v1 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid
 	[0U];
     // ALWAYS at VX_e_m_reg.v:123
     __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__reg_data__v0 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data
-	[3U];
+	[1U];
     __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__reg_data__v1 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data
-	[2U];
-    __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__reg_data__v2 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data
-	[1U];
-    __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__reg_data__v3 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data
-	[0U];
-    // ALWAYS at VX_m_w_reg.v:60
-    __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v0 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result
-	[1U];
-    __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v1 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result
 	[0U];
     // ALWAYS at VX_m_w_reg.v:60
     __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v0 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result
-	[1U];
-    __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v1 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result
 	[0U];
+    // ALWAYS at VX_m_w_reg.v:60
+    __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v0 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result
+	[0U];
+    // ALWAYS at VX_csr_handler.v:34
+    vlTOPp->Vortex__DOT__vx_csr_handler__DOT__decode_csr_address 
+	= vlTOPp->Vortex__DOT__decode_csr_address;
     // ALWAYS at VX_d_e_reg.v:133
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed 
 	= (0xfffffU & ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
@@ -310,9 +264,6 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 						 >> 0xcU)
 						 : 0U))));
     // ALWAYS at VX_csr_handler.v:34
-    vlTOPp->Vortex__DOT__vx_csr_handler__DOT__decode_csr_address 
-	= vlTOPp->Vortex__DOT__decode_csr_address;
-    // ALWAYS at VX_csr_handler.v:34
     vlTOPp->Vortex__DOT__vx_csr_handler__DOT__cycle 
 	= (VL_ULL(1) + vlTOPp->Vortex__DOT__vx_csr_handler__DOT__cycle);
     // ALWAYS at VX_csr_handler.v:34
@@ -320,6 +271,10 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 	vlTOPp->Vortex__DOT__vx_csr_handler__DOT__instret 
 	    = (VL_ULL(1) + vlTOPp->Vortex__DOT__vx_csr_handler__DOT__instret);
     }
+    // ALWAYS at VX_e_m_reg.v:123
+    __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v0 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result
+	[0U];
     // ALWAYS at VX_d_e_reg.v:133
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rs2_src = 
 	(1U & ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
@@ -327,62 +282,40 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 			       | (0x23U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)))
 			       ? 1U : 0U))));
     // ALWAYS at VX_e_m_reg.v:123
-    __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v0 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result
-	[1U];
-    __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v1 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result
-	[0U];
-    // ALWAYS at VX_e_m_reg.v:123
     vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type 
 	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__branch_type;
     // ALWAYS at VX_d_e_reg.v:133
     __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v0 
-	= ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
-	    ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid_z
-	   [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid
-	   [1U]);
-    __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v1 
 	= ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
 	    ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid_z
 	   [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid
 	   [0U]);
     // ALWAYS at VX_e_m_reg.v:123
-    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__mem_read 
-	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__mem_read;
+    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__curr_PC = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC;
     // ALWAYS at VX_e_m_reg.v:123
     vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__mem_write 
 	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__mem_write;
     // ALWAYS at VX_e_m_reg.v:123
-    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal;
+    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__mem_read 
+	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__mem_read;
     // ALWAYS at VX_e_m_reg.v:123
-    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__curr_PC = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC;
+    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal;
+    // ALWAYS at VX_m_w_reg.v:60
+    vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next;
     // ALWAYS at VX_e_m_reg.v:123
     vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_offset 
 	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed;
-    // ALWAYS at VX_m_w_reg.v:60
-    vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next;
     // ALWAYS at VX_e_m_reg.v:123
     vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal_dest 
 	= (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data
 	   [0U] + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal_offset);
     // ALWAYS at VX_register_file.v:36
-    if ((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) 
-	  & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) 
-	 & vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid
-	 [1U])) {
-	__Vdlyvval__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers__v0 
-	    = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data
-	    [1U];
-	__Vdlyvset__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers__v0 = 1U;
-	__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers__v0 
-	    = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd;
-    }
-    // ALWAYS at VX_register_file.v:36
-    if ((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) 
-	  & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) 
-	 & vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid
-	 [0U])) {
+    if (VL_UNLIKELY((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) 
+		      & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) 
+		     & vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid
+		     [0U]))) {
+	VL_WRITEF("Writing %x to %2#\n",32,vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data
+		  [0U],5,vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd);
 	__Vdlyvval__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers__v0 
 	    = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data
 	    [0U];
@@ -400,69 +333,38 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
     }
     // ALWAYS at VX_d_e_reg.v:133
     __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__reg_data__v0 
-	= ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
-	    ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z
-	   [3U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data
-	   [3U]);
-    __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__reg_data__v1 
-	= ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
-	    ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z
-	   [2U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data
-	   [2U]);
-    __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__reg_data__v2 
 	= ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
 	    ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z
 	   [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data
 	   [1U]);
-    __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__reg_data__v3 
+    __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__reg_data__v1 
 	= ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
 	    ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z
 	   [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data
 	   [0U]);
     // ALWAYSPOST at VX_m_w_reg.v:69
-    vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid[1U] 
-	= __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v0;
     vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid[0U] 
-	= __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v1;
+	= __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v0;
     // ALWAYSPOST at VX_e_m_reg.v:142
-    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid[1U] 
-	= __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v0;
     vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid[0U] 
-	= __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v1;
+	= __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v0;
     // ALWAYSPOST at VX_e_m_reg.v:133
-    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data[3U] 
-	= __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__reg_data__v0;
-    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data[2U] 
-	= __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__reg_data__v1;
     vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data[1U] 
-	= __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__reg_data__v2;
+	= __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__reg_data__v0;
     vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data[0U] 
-	= __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__reg_data__v3;
-    // ALWAYSPOST at VX_m_w_reg.v:62
-    vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result[1U] 
-	= __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v0;
-    vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result[0U] 
-	= __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v1;
+	= __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__reg_data__v1;
     // ALWAYSPOST at VX_m_w_reg.v:63
-    vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result[1U] 
-	= __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v0;
     vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result[0U] 
-	= __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v1;
+	= __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v0;
+    // ALWAYSPOST at VX_m_w_reg.v:62
+    vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result[0U] 
+	= __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v0;
     // ALWAYSPOST at VX_e_m_reg.v:125
-    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result[1U] 
-	= __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v0;
     vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result[0U] 
-	= __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v1;
+	= __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v0;
     // ALWAYSPOST at VX_d_e_reg.v:154
-    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid[1U] 
-	= __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v0;
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid[0U] 
-	= __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v1;
-    // ALWAYSPOST at VX_register_file.v:39
-    if (__Vdlyvset__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers__v0) {
-	vlTOPp->Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers[__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers__v0] 
-	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers__v0;
-    }
+	= __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v0;
     // ALWAYSPOST at VX_register_file.v:39
     if (__Vdlyvset__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers__v0) {
 	vlTOPp->Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers[__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers__v0] 
@@ -474,53 +376,28 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 	    = __Vdlyvval__Vortex__DOT__vx_csr_handler__DOT__csr__v0;
     }
     // ALWAYSPOST at VX_d_e_reg.v:138
-    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data[3U] 
-	= __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__reg_data__v0;
-    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data[2U] 
-	= __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__reg_data__v1;
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data[1U] 
-	= __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__reg_data__v2;
+	= __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__reg_data__v0;
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data[0U] 
-	= __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__reg_data__v3;
-    vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[1U] 
-	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid
-	[1U];
+	= __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__reg_data__v1;
     vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[0U] 
 	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid
 	[0U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[1U] 
-	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid
-	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[0U] 
 	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid
 	[0U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data[3U] 
-	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data
-	[3U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data[2U] 
-	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data
-	[2U];
     vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data[1U] 
 	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data
 	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data[0U] 
 	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data
 	[0U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[1U] 
-	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result
-	[1U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[0U] 
-	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result
-	[0U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[1U] 
-	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result
-	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[0U] 
 	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result
 	[0U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[1U] 
-	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result
-	[1U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[0U] 
+	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result
+	[0U];
     vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[0U] 
 	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result
 	[0U];
@@ -528,19 +405,13 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__branch_type 
 	= ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
 	    ? 0U : (IData)(vlTOPp->Vortex__DOT__decode_branch_type));
-    vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[1U] 
-	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid
-	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[0U] 
 	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid
 	[0U];
-    vlTOPp->out_cache_driver_in_mem_read = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__mem_read;
     // ALWAYS at VX_d_e_reg.v:133
-    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__mem_read 
-	= (7U & ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
-		  ? 7U : ((3U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))
-			   ? (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
-			      >> 0xcU) : 7U)));
+    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC = 
+	((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
+	  ? 0U : vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC);
     vlTOPp->out_cache_driver_in_mem_write = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__mem_write;
     // ALWAYS at VX_d_e_reg.v:133
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__mem_write 
@@ -548,6 +419,13 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 		  ? 7U : ((0x23U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))
 			   ? (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
 			      >> 0xcU) : 7U)));
+    vlTOPp->out_cache_driver_in_mem_read = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__mem_read;
+    // ALWAYS at VX_d_e_reg.v:133
+    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__mem_read 
+	= (7U & ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
+		  ? 7U : ((3U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))
+			   ? (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
+			      >> 0xcU) : 7U)));
     // ALWAYS at VX_d_e_reg.v:133
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal = ((~ (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)) 
 						 & ((0x6fU 
@@ -572,10 +450,12 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 								(0xfffU 
 								 & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
 								    >> 0x14U))))))));
-    // ALWAYS at VX_d_e_reg.v:133
-    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC = 
-	((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
-	  ? 0U : vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC);
+    vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data[0U] 
+	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next;
+    vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[0U] 
+	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next;
+    // ALWAYS at VX_e_m_reg.v:123
+    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out;
     vlTOPp->Vortex__DOT__memory_branch_dest = (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__curr_PC 
 					       + (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_offset 
 						  << 1U));
@@ -583,16 +463,6 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed 
 	= ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
 	    ? 0xdeadbeefU : vlTOPp->Vortex__DOT__decode_itype_immed);
-    vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data[0U] 
-	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next;
-    vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data[1U] 
-	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next;
-    vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[0U] 
-	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next;
-    vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[1U] 
-	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next;
-    // ALWAYS at VX_e_m_reg.v:123
-    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out;
     // ALWAYS at VX_d_e_reg.v:133
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal_offset 
 	= ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
@@ -645,48 +515,26 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 		    ? (vlTOPp->Vortex__DOT__csr_decode_csr_data 
 		       & ((IData)(0xffffffffU) - vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__csr_mask))
 		    : 0xdeadbeefU)));
-    vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data[3U] 
-	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data
-	[3U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data[2U] 
-	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data
-	[2U];
     vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data[1U] 
 	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data
 	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data[0U] 
 	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data
 	[0U];
-    vlTOPp->Vortex__DOT__m_w_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid
-	[1U];
     vlTOPp->Vortex__DOT__m_w_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid
 	[0U];
-    vlTOPp->Vortex__DOT__e_m_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid
-	[1U];
     vlTOPp->Vortex__DOT__e_m_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid
 	[0U];
-    vlTOPp->Vortex__DOT__e_m_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data
-	[3U];
-    vlTOPp->Vortex__DOT__e_m_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data
-	[2U];
     vlTOPp->Vortex__DOT__e_m_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data
 	[1U];
     vlTOPp->Vortex__DOT__e_m_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data
 	[0U];
-    vlTOPp->Vortex__DOT__m_w_alu_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result
-	[1U];
-    vlTOPp->Vortex__DOT__m_w_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result
-	[0U];
-    vlTOPp->Vortex__DOT__m_w_mem_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result
-	[1U];
     vlTOPp->Vortex__DOT__m_w_mem_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result
 	[0U];
-    vlTOPp->Vortex__DOT__e_m_alu_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result
-	[1U];
+    vlTOPp->Vortex__DOT__m_w_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result
+	[0U];
     vlTOPp->Vortex__DOT__e_m_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result
 	[0U];
-    vlTOPp->Vortex__DOT__d_e_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid
-	[1U];
     vlTOPp->Vortex__DOT__d_e_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid
 	[0U];
     vlTOPp->Vortex__DOT__csr_decode_csr_data = ((0xc00U 
@@ -711,48 +559,26 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 						    : 
 						   vlTOPp->Vortex__DOT__vx_csr_handler__DOT__csr
 						   [vlTOPp->Vortex__DOT__vx_csr_handler__DOT__decode_csr_address]))));
-    vlTOPp->Vortex__DOT__d_e_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data
-	[3U];
-    vlTOPp->Vortex__DOT__d_e_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data
-	[2U];
     vlTOPp->Vortex__DOT__d_e_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data
 	[1U];
     vlTOPp->Vortex__DOT__d_e_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data
 	[0U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[1U] 
-	= vlTOPp->Vortex__DOT__m_w_valid[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[0U] 
 	= vlTOPp->Vortex__DOT__m_w_valid[0U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid[1U] 
-	= vlTOPp->Vortex__DOT__e_m_valid[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid[0U] 
 	= vlTOPp->Vortex__DOT__e_m_valid[0U];
     vlTOPp->Vortex__DOT__use_rd2[0U] = vlTOPp->Vortex__DOT__e_m_reg_data
 	[1U];
-    vlTOPp->Vortex__DOT__use_rd2[1U] = vlTOPp->Vortex__DOT__e_m_reg_data
-	[3U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[1U] 
-	= vlTOPp->Vortex__DOT__m_w_alu_result[1U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[0U] 
-	= vlTOPp->Vortex__DOT__m_w_alu_result[0U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[1U] 
-	= vlTOPp->Vortex__DOT__m_w_alu_result[1U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[0U] 
-	= vlTOPp->Vortex__DOT__m_w_alu_result[0U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[1U] 
-	= vlTOPp->Vortex__DOT__m_w_mem_result[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[0U] 
 	= vlTOPp->Vortex__DOT__m_w_mem_result[0U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[1U] 
-	= vlTOPp->Vortex__DOT__m_w_mem_result[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[0U] 
 	= vlTOPp->Vortex__DOT__m_w_mem_result[0U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result[1U] 
-	= vlTOPp->Vortex__DOT__e_m_alu_result[1U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[0U] 
+	= vlTOPp->Vortex__DOT__m_w_alu_result[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[0U] 
+	= vlTOPp->Vortex__DOT__m_w_alu_result[0U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result[0U] 
 	= vlTOPp->Vortex__DOT__e_m_alu_result[0U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid[1U] 
-	= vlTOPp->Vortex__DOT__d_e_valid[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid[0U] 
 	= vlTOPp->Vortex__DOT__d_e_valid[0U];
     vlTOPp->Vortex__DOT__execute_branch_stall = ((0U 
@@ -760,8 +586,6 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 						 | (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal));
     vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[0U] 
 	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next;
-    vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[1U] 
-	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next;
     // ALWAYS at VX_d_e_reg.v:133
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out 
 	= ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
@@ -795,37 +619,18 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 					     & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)))
 		     ? (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__mul_alu)
 		     : (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__temp_final_alu)));
-    vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data[3U] 
-	= vlTOPp->Vortex__DOT__d_e_reg_data[3U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data[2U] 
-	= vlTOPp->Vortex__DOT__d_e_reg_data[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data[1U] 
 	= vlTOPp->Vortex__DOT__d_e_reg_data[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data[0U] 
 	= vlTOPp->Vortex__DOT__d_e_reg_data[0U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[1U] 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid
-	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[0U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid
 	[0U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid[1U] 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid
-	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid[0U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid
 	[0U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2[1U] 
-	= vlTOPp->Vortex__DOT__use_rd2[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2[0U] 
 	= vlTOPp->Vortex__DOT__use_rd2[0U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data[1U] 
-	= ((3U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
-	    ? vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data
-	   [1U] : ((1U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
-		    ? vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result
-		   [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result
-		   [1U]));
     vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data[0U] 
 	= ((3U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
 	    ? vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data
@@ -833,9 +638,6 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 		    ? vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result
 		   [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result
 		   [0U]));
-    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[1U] 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
-	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[0U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
 	[0U];
@@ -885,24 +687,12 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 						       == 
 						       vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
 						       [0U])))));
-    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result[1U] 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
-	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result[0U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
 	[0U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid[1U] 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid
-	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid[0U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid
 	[0U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data[3U] 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data
-	[3U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data[2U] 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data
-	[2U];
     vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data[1U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data
 	[1U];
@@ -915,48 +705,24 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
     vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data[0U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data
 	[0U];
-    vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data[1U] 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data
-	[3U];
-    vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data[0U] 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data
-	[2U];
-    vlTOPp->out_cache_driver_in_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid
-	[1U];
     vlTOPp->out_cache_driver_in_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid
 	[0U];
-    vlTOPp->Vortex__DOT__memory_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid
-	[1U];
     vlTOPp->Vortex__DOT__memory_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid
 	[0U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[1U] 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2
-	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[0U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2
 	[0U];
-    vlTOPp->Vortex__DOT__writeback_write_data[1U] = 
-	vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data
-	[1U];
     vlTOPp->Vortex__DOT__writeback_write_data[0U] = 
 	vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data
 	[0U];
-    vlTOPp->out_cache_driver_in_address[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address
-	[1U];
     vlTOPp->out_cache_driver_in_address[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address
 	[0U];
-    vlTOPp->Vortex__DOT__memory_alu_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result
-	[1U];
     vlTOPp->Vortex__DOT__memory_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result
 	[0U];
-    vlTOPp->Vortex__DOT__execute_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid
-	[1U];
     vlTOPp->Vortex__DOT__execute_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid
 	[0U];
     vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[0U] 
 	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out;
-    vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[1U] 
-	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out;
     // ALWAYS at VX_d_e_reg.v:133
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd = (0x1fU 
 						& ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
@@ -1009,10 +775,6 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 						    | (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_csr))
 						    ? 1U
 						    : 0U))));
-    vlTOPp->Vortex__DOT__execute_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data
-	[3U];
-    vlTOPp->Vortex__DOT__execute_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data
-	[2U];
     vlTOPp->Vortex__DOT__execute_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data
 	[1U];
     vlTOPp->Vortex__DOT__execute_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data
@@ -1022,41 +784,19 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 	    ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed
 	    : vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data
 	   [1U]);
-    vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2 
-	= ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rs2_src)
-	    ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed
-	    : vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data
-	   [1U]);
-    vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[1U] 
-	= vlTOPp->Vortex__DOT__memory_valid[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[0U] 
 	= vlTOPp->Vortex__DOT__memory_valid[0U];
-    vlTOPp->out_cache_driver_in_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data
-	[1U];
     vlTOPp->out_cache_driver_in_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data
 	[0U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data[1U] 
-	= vlTOPp->Vortex__DOT__writeback_write_data
-	[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data[0U] 
 	= vlTOPp->Vortex__DOT__writeback_write_data
 	[0U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[1U] 
-	= vlTOPp->Vortex__DOT__memory_alu_result[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[0U] 
 	= vlTOPp->Vortex__DOT__memory_alu_result[0U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[1U] 
-	= vlTOPp->Vortex__DOT__memory_alu_result[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[0U] 
 	= vlTOPp->Vortex__DOT__memory_alu_result[0U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[1U] 
-	= vlTOPp->Vortex__DOT__execute_valid[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[0U] 
 	= vlTOPp->Vortex__DOT__execute_valid[0U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data[3U] 
-	= vlTOPp->Vortex__DOT__execute_reg_data[3U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data[2U] 
-	= vlTOPp->Vortex__DOT__execute_reg_data[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data[1U] 
 	= vlTOPp->Vortex__DOT__execute_reg_data[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data[0U] 
@@ -1066,11 +806,6 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 					      vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data
 					      [0U]), 
 		      VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2));
-    vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__mult_signed_result 
-	= VL_MULS_QQQ(64,64,64, VL_EXTENDS_QI(64,32, 
-					      vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data
-					      [0U]), 
-		      VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2));
     // ALWAYS at VX_alu.v:47
     vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_alu__out_alu_result 
 	= ((0x10U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
@@ -1198,147 +933,12 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 						 (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data
 						  [0U] 
 						  + vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2))))));
-    // ALWAYS at VX_alu.v:47
-    vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_alu__out_alu_result 
-	= ((0x10U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-	    ? ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-	        ? 0U : ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-			 ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-			     ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-				 ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)
-				     ? vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data
-				    [0U] : VL_MODDIV_III(32, 
-							 vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data
-							 [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2))
-				 : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)
-				     ? vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data
-				    [0U] : VL_MODDIVS_III(32, 
-							  vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data
-							  [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)))
-			     : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-				 ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)
-				     ? 0xffffffffU : 
-				    VL_DIV_III(32, 
-					       vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data
-					       [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2))
-				 : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)
-				     ? 0xffffffffU : 
-				    VL_DIVS_III(32, 
-						vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data
-						[0U], vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2))))
-			 : ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-			     ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-				 ? (IData)((((QData)((IData)(
-							     vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data
-							     [0U])) 
-					     * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2))) 
-					    >> 0x20U))
-				 : (IData)((((((QData)((IData)(
-							       VL_NEGATE_I((IData)(
-										(1U 
-										& (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data
-										[0U] 
-										>> 0x1fU)))))) 
-					       << 0x20U) 
-					      | (QData)((IData)(
-								vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data
-								[0U]))) 
-					     * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2))) 
-					    >> 0x20U)))
-			     : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-				 ? (IData)((vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__mult_signed_result 
-					    >> 0x20U))
-				 : (IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__mult_signed_result)))))
-	    : ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-	        ? ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-		    ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-		        ? vlTOPp->Vortex__DOT__csr_decode_csr_data
-		        : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-			    ? vlTOPp->Vortex__DOT__csr_decode_csr_data
-			    : (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC 
-			       + (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed 
-				  << 0xcU)))) : ((2U 
-						  & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-						  ? 
-						 ((1U 
-						   & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-						   ? 
-						  (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed 
-						   << 0xcU)
-						   : 
-						  ((vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data
-						    [0U] 
-						    >= vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)
-						    ? 0U
-						    : 0xffffffffU))
-						  : 
-						 ((1U 
-						   & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-						   ? 
-						  (vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2 
-						   & vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data
-						   [0U])
-						   : 
-						  (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data
-						   [0U] 
-						   | vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2))))
-	        : ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-		    ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-		        ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-			    ? VL_SHIFTRS_III(32,32,5, 
-					     vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data
-					     [0U], 
-					     (0x1fU 
-					      & vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2))
-			    : (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data
-			       [0U] >> (0x1fU & vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)))
-		        : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-			    ? (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data
-			       [0U] ^ vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)
-			    : ((vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data
-				[0U] < vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)
-			        ? 1U : 0U))) : ((2U 
-						 & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-						 ? 
-						((1U 
-						  & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-						  ? 
-						 (VL_LTS_III(1,32,32, 
-							     vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data
-							     [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)
-						   ? 1U
-						   : 0U)
-						  : 
-						 (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data
-						  [0U] 
-						  << 
-						  (0x1fU 
-						   & vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)))
-						 : 
-						((1U 
-						  & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-						  ? 
-						 (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data
-						  [0U] 
-						  - vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)
-						  : 
-						 (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data
-						  [0U] 
-						  + vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2))))));
     vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result[0U] 
 	= vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_alu__out_alu_result;
-    vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result[0U] 
-	= vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_alu__out_alu_result;
-    vlTOPp->Vortex__DOT__execute_alu_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result
-	[1U];
     vlTOPp->Vortex__DOT__execute_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result
 	[0U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[1U] 
-	= vlTOPp->Vortex__DOT__execute_alu_result[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[0U] 
 	= vlTOPp->Vortex__DOT__execute_alu_result[0U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[1U] 
-	= vlTOPp->Vortex__DOT__execute_alu_result[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[0U] 
 	= vlTOPp->Vortex__DOT__execute_alu_result[0U];
 }
@@ -1347,26 +947,15 @@ VL_INLINE_OPT void VVortex::_combo__TOP__3(VVortex__Syms* __restrict vlSymsp) {
     VL_DEBUG_IF(VL_DBG_MSGF("+    VVortex::_combo__TOP__3\n"); );
     VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
     // Body
-    vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[1U] 
-	= vlTOPp->in_cache_driver_out_data[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[0U] 
 	= vlTOPp->in_cache_driver_out_data[0U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result[1U] 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data
-	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result[0U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data
 	[0U];
-    vlTOPp->Vortex__DOT__memory_mem_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result
-	[1U];
     vlTOPp->Vortex__DOT__memory_mem_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result
 	[0U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[1U] 
-	= vlTOPp->Vortex__DOT__memory_mem_result[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[0U] 
 	= vlTOPp->Vortex__DOT__memory_mem_result[0U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[1U] 
-	= vlTOPp->Vortex__DOT__memory_mem_result[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[0U] 
 	= vlTOPp->Vortex__DOT__memory_mem_result[0U];
 }
@@ -1375,39 +964,21 @@ void VVortex::_settle__TOP__4(VVortex__Syms* __restrict vlSymsp) {
     VL_DEBUG_IF(VL_DBG_MSGF("+    VVortex::_settle__TOP__4\n"); );
     VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
     // Body
-    vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[1U] 
-	= vlTOPp->in_cache_driver_out_data[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[0U] 
 	= vlTOPp->in_cache_driver_out_data[0U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[1U] 
-	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid
-	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[0U] 
 	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid
 	[0U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register[0U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_register_file__out_src2_data;
-    vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register[1U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file__out_src2_data;
-    vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register[0U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_register_file__out_src1_data;
-    vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register[1U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file__out_src1_data;
-    vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[1U] 
-	= vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid
-	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[0U] 
 	= vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid
 	[0U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[1U] 
-	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result
-	[1U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register[0U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_register_file__out_src2_data;
+    vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register[0U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_register_file__out_src1_data;
     vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[0U] 
 	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result
 	[0U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[1U] 
-	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result
-	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[0U] 
 	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result
 	[0U];
@@ -1429,7 +1000,7 @@ void VVortex::_settle__TOP__4(VVortex__Syms* __restrict vlSymsp) {
 						  (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
 						   >> 0x14U)
 						   : 0x55U));
-    // ALWAYS at VX_decode.v:357
+    // ALWAYS at VX_decode.v:364
     vlTOPp->__Vtableidx1 = (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
 				  >> 0xcU));
     vlTOPp->Vortex__DOT__vx_decode__DOT__mul_alu = 
@@ -1455,7 +1026,7 @@ void VVortex::_settle__TOP__4(VVortex__Syms* __restrict vlSymsp) {
 						      (7U 
 						       & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
 							  >> 0xcU))));
-    // ALWAYS at VX_decode.v:307
+    // ALWAYS at VX_decode.v:314
     vlTOPp->Vortex__DOT__decode_branch_type = ((0x63U 
 						== 
 						(0x7fU 
@@ -1486,29 +1057,18 @@ void VVortex::_settle__TOP__4(VVortex__Syms* __restrict vlSymsp) {
 						      ? 2U
 						      : 1U)))
 					        : 0U);
-    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result[1U] 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data
-	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result[0U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data
 	[0U];
-    vlTOPp->Vortex__DOT__m_w_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid
-	[1U];
     vlTOPp->Vortex__DOT__m_w_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid
 	[0U];
-    vlTOPp->Vortex__DOT__f_d_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid
-	[1U];
     vlTOPp->Vortex__DOT__f_d_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid
 	[0U];
-    vlTOPp->Vortex__DOT__m_w_alu_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result
-	[1U];
     vlTOPp->Vortex__DOT__m_w_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result
 	[0U];
-    vlTOPp->Vortex__DOT__m_w_mem_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result
-	[1U];
     vlTOPp->Vortex__DOT__m_w_mem_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result
 	[0U];
-    // ALWAYS at VX_decode.v:296
+    // ALWAYS at VX_decode.v:303
     vlTOPp->Vortex__DOT__decode_itype_immed = ((0x40U 
 						& vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)
 					        ? (
@@ -1724,54 +1284,29 @@ void VVortex::_settle__TOP__4(VVortex__Syms* __restrict vlSymsp) {
 							  >> 0x19U)))
 						      ? 0U
 						      : 1U))))))))));
-    vlTOPp->Vortex__DOT__memory_mem_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result
-	[1U];
     vlTOPp->Vortex__DOT__memory_mem_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result
 	[0U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[1U] 
-	= vlTOPp->Vortex__DOT__m_w_valid[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[0U] 
 	= vlTOPp->Vortex__DOT__m_w_valid[0U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid[1U] 
-	= vlTOPp->Vortex__DOT__f_d_valid[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid[0U] 
 	= vlTOPp->Vortex__DOT__f_d_valid[0U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[1U] 
-	= vlTOPp->Vortex__DOT__m_w_alu_result[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[0U] 
 	= vlTOPp->Vortex__DOT__m_w_alu_result[0U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[1U] 
-	= vlTOPp->Vortex__DOT__m_w_alu_result[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[0U] 
 	= vlTOPp->Vortex__DOT__m_w_alu_result[0U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[1U] 
-	= vlTOPp->Vortex__DOT__m_w_mem_result[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[0U] 
 	= vlTOPp->Vortex__DOT__m_w_mem_result[0U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[1U] 
-	= vlTOPp->Vortex__DOT__m_w_mem_result[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[0U] 
 	= vlTOPp->Vortex__DOT__m_w_mem_result[0U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[1U] 
-	= vlTOPp->Vortex__DOT__memory_mem_result[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[0U] 
 	= vlTOPp->Vortex__DOT__memory_mem_result[0U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[1U] 
-	= vlTOPp->Vortex__DOT__memory_mem_result[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[0U] 
 	= vlTOPp->Vortex__DOT__memory_mem_result[0U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid[1U] 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid
-	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid[0U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid
 	[0U];
-    vlTOPp->Vortex__DOT__decode_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid
-	[1U];
     vlTOPp->Vortex__DOT__decode_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid
 	[0U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[1U] 
-	= vlTOPp->Vortex__DOT__decode_valid[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[0U] 
 	= vlTOPp->Vortex__DOT__decode_valid[0U];
 }
@@ -1780,32 +1315,25 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__5(VVortex__Syms* __restrict vlSymsp)
     VL_DEBUG_IF(VL_DBG_MSGF("+    VVortex::_sequent__TOP__5\n"); );
     VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
     // Body
-    // ALWAYS at VX_register_file.v:43
-    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file__out_src2_data 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers
-	[(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
-		   >> 0x14U))];
+    // ALWAYS at VX_writeback.v:21
+    if (VL_UNLIKELY((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)))) {
+	VL_WRITEF("(%x) WB Data: %x, to register: %2#\n",
+		  32,(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next 
+		      - (IData)(4U)),32,vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result
+		  [0U],5,vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd);
+    }
     // ALWAYS at VX_register_file.v:43
     vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_register_file__out_src2_data 
 	= vlTOPp->Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers
 	[(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
 		   >> 0x14U))];
     // ALWAYS at VX_register_file.v:43
-    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file__out_src1_data 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers
-	[(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
-		   >> 0xfU))];
-    // ALWAYS at VX_register_file.v:43
     vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_register_file__out_src1_data 
 	= vlTOPp->Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers
 	[(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
 		   >> 0xfU))];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register[1U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file__out_src2_data;
     vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register[0U] 
 	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_register_file__out_src2_data;
-    vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register[1U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file__out_src1_data;
     vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register[0U] 
 	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_register_file__out_src1_data;
 }
@@ -1815,10 +1343,7 @@ void VVortex::_initial__TOP__6(VVortex__Syms* __restrict vlSymsp) {
     VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
     // Body
     // INITIAL at VX_fetch.v:51
-    vlTOPp->Vortex__DOT__vx_fetch__DOT__valid = (1U 
-						 | (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__valid));
-    vlTOPp->Vortex__DOT__vx_fetch__DOT__valid = (1U 
-						 & (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__valid));
+    vlTOPp->Vortex__DOT__vx_fetch__DOT__valid = 1U;
     vlTOPp->Vortex__DOT__vx_fetch__DOT__stall_reg = 0U;
     vlTOPp->Vortex__DOT__vx_fetch__DOT__delay_reg = 0U;
     vlTOPp->Vortex__DOT__vx_fetch__DOT__old = 0U;
@@ -1852,19 +1377,12 @@ void VVortex::_initial__TOP__6(VVortex__Syms* __restrict vlSymsp) {
     vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data[0U] = 0U;
     vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid[0U] = 0U;
     vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result[0U] = 0U;
-    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data[1U] = 0U;
-    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid[1U] = 0U;
-    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result[1U] = 0U;
     // INITIAL at VX_d_e_reg.v:79
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd = 0U;
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data[0U] = 0U;
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[0U] = 0U;
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid[0U] = 0U;
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid_z[0U] = 0U;
-    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data[1U] = 0U;
-    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[1U] = 0U;
-    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid[1U] = 0U;
-    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid_z[1U] = 0U;
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op = 0U;
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb = 0U;
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out = 0U;
@@ -1886,8 +1404,6 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__7(VVortex__Syms* __restrict vlSymsp)
     VL_DEBUG_IF(VL_DBG_MSGF("+    VVortex::_sequent__TOP__7\n"); );
     VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
     // Body
-    vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[1U] 
-	= vlTOPp->Vortex__DOT__decode_valid[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[0U] 
 	= vlTOPp->Vortex__DOT__decode_valid[0U];
     // ALWAYS at VX_f_d_reg.v:29
@@ -1938,7 +1454,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__7(VVortex__Syms* __restrict vlSymsp)
 						  (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
 						   >> 0x14U)
 						   : 0x55U));
-    // ALWAYS at VX_decode.v:357
+    // ALWAYS at VX_decode.v:364
     vlTOPp->__Vtableidx1 = (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
 				  >> 0xcU));
     vlTOPp->Vortex__DOT__vx_decode__DOT__mul_alu = 
@@ -1964,7 +1480,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__7(VVortex__Syms* __restrict vlSymsp)
 						      (7U 
 						       & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
 							  >> 0xcU))));
-    // ALWAYS at VX_decode.v:307
+    // ALWAYS at VX_decode.v:314
     vlTOPp->Vortex__DOT__decode_branch_type = ((0x63U 
 						== 
 						(0x7fU 
@@ -2005,7 +1521,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__7(VVortex__Syms* __restrict vlSymsp)
 		       >> 0xfU)) == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd)) 
 	    & (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
 			       >> 0xfU)))) & (0U != (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb)));
-    // ALWAYS at VX_decode.v:296
+    // ALWAYS at VX_decode.v:303
     vlTOPp->Vortex__DOT__decode_itype_immed = ((0x40U 
 						& vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)
 					        ? (
@@ -2258,9 +1774,6 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__7(VVortex__Syms* __restrict vlSymsp)
 						!= (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))) 
 	    & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd))) 
 	   & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd)));
-    vlTOPp->Vortex__DOT__forwarding_src2_fwd = (((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd) 
-						 | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd)) 
-						| (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd));
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling 
 	= ((IData)(vlTOPp->Vortex__DOT__forwarding_fwd_stall) 
 	   | (IData)(vlTOPp->Vortex__DOT__execute_branch_stall));
@@ -2279,22 +1792,11 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__7(VVortex__Syms* __restrict vlSymsp)
 							  & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)))) 
 						  | (IData)(vlTOPp->Vortex__DOT__forwarding_fwd_stall)) 
 						 | (IData)(vlTOPp->Vortex__DOT__execute_branch_stall));
-    vlTOPp->Vortex__DOT__forwarding_src1_fwd = (((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd) 
-						 | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd)) 
-						| (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd));
     vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid[0U] 
-	= (1U & ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall)) 
-		 & (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__valid)));
-    vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid[1U] 
-	= (1U & ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall)) 
-		 & ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__valid) 
-		    >> 1U)));
-    vlTOPp->Vortex__DOT__fetch_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid
-	[1U];
+	= ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall)) 
+	   & (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__valid));
     vlTOPp->Vortex__DOT__fetch_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid
 	[0U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[1U] 
-	= vlTOPp->Vortex__DOT__fetch_valid[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[0U] 
 	= vlTOPp->Vortex__DOT__fetch_valid[0U];
 }
@@ -2326,12 +1828,8 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) {
 					    : vlTOPp->Vortex__DOT__vx_fetch__DOT__real_PC)))))));
     vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data[0U] 
 	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next;
-    vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data[1U] 
-	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next;
     vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[0U] 
 	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next;
-    vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[1U] 
-	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next;
     vlTOPp->Vortex__DOT__csr_decode_csr_data = ((0xc00U 
 						 == (IData)(vlTOPp->Vortex__DOT__vx_csr_handler__DOT__decode_csr_address))
 						 ? (IData)(vlTOPp->Vortex__DOT__vx_csr_handler__DOT__cycle)
@@ -2359,59 +1857,34 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) {
     vlTOPp->Vortex__DOT__memory_branch_dest = (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__curr_PC 
 					       + (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_offset 
 						  << 1U));
-    vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[1U] 
-	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid
-	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[0U] 
 	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid
 	[0U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data[3U] 
-	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data
-	[3U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data[2U] 
-	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data
-	[2U];
     vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data[1U] 
 	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data
 	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data[0U] 
 	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__reg_data
 	[0U];
-    vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[0U] 
-	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next;
-    vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[1U] 
-	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next;
-    vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[1U] 
-	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result
-	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[0U] 
 	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result
 	[0U];
+    vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[0U] 
+	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next;
     vlTOPp->Vortex__DOT__execute_branch_stall = ((0U 
 						  != (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__branch_type)) 
 						 | (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal));
-    vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[1U] 
-	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid
-	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[0U] 
 	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid
 	[0U];
-    vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[0U] 
-	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out;
-    vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[1U] 
-	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out;
-    vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data[3U] 
-	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data
-	[3U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data[2U] 
-	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data
-	[2U];
     vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data[1U] 
 	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data
 	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data[0U] 
 	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data
 	[0U];
+    vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[0U] 
+	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out;
     vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd 
 	= ((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
 		       >> 0x14U)) == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd)) 
@@ -2422,13 +1895,6 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) {
 		       >> 0xfU)) == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd)) 
 	    & (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
 			       >> 0xfU)))) & (0U != (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb)));
-    vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data[1U] 
-	= ((3U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
-	    ? vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data
-	   [1U] : ((1U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
-		    ? vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result
-		   [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result
-		   [1U]));
     vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data[0U] 
 	= ((3U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
 	    ? vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data
@@ -2436,30 +1902,16 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) {
 		    ? vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result
 		   [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result
 		   [0U]));
-    vlTOPp->Vortex__DOT__e_m_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid
-	[1U];
     vlTOPp->Vortex__DOT__e_m_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid
 	[0U];
-    vlTOPp->Vortex__DOT__e_m_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data
-	[3U];
-    vlTOPp->Vortex__DOT__e_m_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data
-	[2U];
     vlTOPp->Vortex__DOT__e_m_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data
 	[1U];
     vlTOPp->Vortex__DOT__e_m_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data
 	[0U];
-    vlTOPp->Vortex__DOT__e_m_alu_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result
-	[1U];
     vlTOPp->Vortex__DOT__e_m_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result
 	[0U];
-    vlTOPp->Vortex__DOT__d_e_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid
-	[1U];
     vlTOPp->Vortex__DOT__d_e_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid
 	[0U];
-    vlTOPp->Vortex__DOT__d_e_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data
-	[3U];
-    vlTOPp->Vortex__DOT__d_e_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data
-	[2U];
     vlTOPp->Vortex__DOT__d_e_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data
 	[1U];
     vlTOPp->Vortex__DOT__d_e_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data
@@ -2477,32 +1929,17 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) {
 	     & (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
 				>> 0xfU)))) & (0U != (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb))) 
 	   & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd)));
-    vlTOPp->Vortex__DOT__writeback_write_data[1U] = 
-	vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data
-	[1U];
     vlTOPp->Vortex__DOT__writeback_write_data[0U] = 
 	vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data
 	[0U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid[1U] 
-	= vlTOPp->Vortex__DOT__e_m_valid[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid[0U] 
 	= vlTOPp->Vortex__DOT__e_m_valid[0U];
     vlTOPp->Vortex__DOT__use_rd2[0U] = vlTOPp->Vortex__DOT__e_m_reg_data
 	[1U];
-    vlTOPp->Vortex__DOT__use_rd2[1U] = vlTOPp->Vortex__DOT__e_m_reg_data
-	[3U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result[1U] 
-	= vlTOPp->Vortex__DOT__e_m_alu_result[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result[0U] 
 	= vlTOPp->Vortex__DOT__e_m_alu_result[0U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid[1U] 
-	= vlTOPp->Vortex__DOT__d_e_valid[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid[0U] 
 	= vlTOPp->Vortex__DOT__d_e_valid[0U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data[3U] 
-	= vlTOPp->Vortex__DOT__d_e_reg_data[3U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data[2U] 
-	= vlTOPp->Vortex__DOT__d_e_reg_data[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data[1U] 
 	= vlTOPp->Vortex__DOT__d_e_reg_data[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data[0U] 
@@ -2531,31 +1968,17 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) {
 						!= (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))) 
 	    & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd))) 
 	   & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd)));
-    vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data[1U] 
-	= vlTOPp->Vortex__DOT__writeback_write_data
-	[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data[0U] 
 	= vlTOPp->Vortex__DOT__writeback_write_data
 	[0U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[1U] 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid
-	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[0U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid
 	[0U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid[1U] 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid
-	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid[0U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid
 	[0U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2[1U] 
-	= vlTOPp->Vortex__DOT__use_rd2[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2[0U] 
 	= vlTOPp->Vortex__DOT__use_rd2[0U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[1U] 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
-	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[0U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
 	[0U];
@@ -2605,24 +2028,12 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) {
 						       == 
 						       vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
 						       [0U])))));
-    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result[1U] 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
-	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result[0U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
 	[0U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid[1U] 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid
-	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid[0U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid
 	[0U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data[3U] 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data
-	[3U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data[2U] 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data
-	[2U];
     vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data[1U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data
 	[1U];
@@ -2635,15 +2046,6 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) {
     vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data[0U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data
 	[0U];
-    vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data[1U] 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data
-	[3U];
-    vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data[0U] 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_reg_data
-	[2U];
-    vlTOPp->Vortex__DOT__forwarding_src2_fwd = (((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd) 
-						 | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd)) 
-						| (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd));
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling 
 	= ((IData)(vlTOPp->Vortex__DOT__forwarding_fwd_stall) 
 	   | (IData)(vlTOPp->Vortex__DOT__execute_branch_stall));
@@ -2662,25 +2064,13 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) {
 							  & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)))) 
 						  | (IData)(vlTOPp->Vortex__DOT__forwarding_fwd_stall)) 
 						 | (IData)(vlTOPp->Vortex__DOT__execute_branch_stall));
-    vlTOPp->Vortex__DOT__forwarding_src1_fwd = (((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd) 
-						 | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd)) 
-						| (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd));
-    vlTOPp->out_cache_driver_in_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid
-	[1U];
     vlTOPp->out_cache_driver_in_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid
 	[0U];
-    vlTOPp->Vortex__DOT__memory_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid
-	[1U];
     vlTOPp->Vortex__DOT__memory_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid
 	[0U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[1U] 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2
-	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[0U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2
 	[0U];
-    vlTOPp->out_cache_driver_in_address[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address
-	[1U];
     vlTOPp->out_cache_driver_in_address[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address
 	[0U];
     // ALWAYS at VX_fetch.v:110
@@ -2693,18 +2083,10 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) {
 						     & (~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__delay_reg)))
 						     ? vlTOPp->Vortex__DOT__memory_branch_dest
 						     : vlTOPp->Vortex__DOT__vx_fetch__DOT__PC_to_use));
-    vlTOPp->Vortex__DOT__memory_alu_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result
-	[1U];
     vlTOPp->Vortex__DOT__memory_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result
 	[0U];
-    vlTOPp->Vortex__DOT__execute_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid
-	[1U];
     vlTOPp->Vortex__DOT__execute_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid
 	[0U];
-    vlTOPp->Vortex__DOT__execute_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data
-	[3U];
-    vlTOPp->Vortex__DOT__execute_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data
-	[2U];
     vlTOPp->Vortex__DOT__execute_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data
 	[1U];
     vlTOPp->Vortex__DOT__execute_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_reg_data
@@ -2714,43 +2096,20 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) {
 	    ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed
 	    : vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data
 	   [1U]);
-    vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2 
-	= ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rs2_src)
-	    ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed
-	    : vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data
-	   [1U]);
     vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid[0U] 
-	= (1U & ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall)) 
-		 & (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__valid)));
-    vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid[1U] 
-	= (1U & ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall)) 
-		 & ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__valid) 
-		    >> 1U)));
-    vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[1U] 
-	= vlTOPp->Vortex__DOT__memory_valid[1U];
+	= ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall)) 
+	   & (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__valid));
     vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[0U] 
 	= vlTOPp->Vortex__DOT__memory_valid[0U];
-    vlTOPp->out_cache_driver_in_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data
-	[1U];
     vlTOPp->out_cache_driver_in_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data
 	[0U];
     vlTOPp->curr_PC = vlTOPp->Vortex__DOT__vx_fetch__DOT__temp_PC;
-    vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[1U] 
-	= vlTOPp->Vortex__DOT__memory_alu_result[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[0U] 
 	= vlTOPp->Vortex__DOT__memory_alu_result[0U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[1U] 
-	= vlTOPp->Vortex__DOT__memory_alu_result[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[0U] 
 	= vlTOPp->Vortex__DOT__memory_alu_result[0U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[1U] 
-	= vlTOPp->Vortex__DOT__execute_valid[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[0U] 
 	= vlTOPp->Vortex__DOT__execute_valid[0U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data[3U] 
-	= vlTOPp->Vortex__DOT__execute_reg_data[3U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data[2U] 
-	= vlTOPp->Vortex__DOT__execute_reg_data[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data[1U] 
 	= vlTOPp->Vortex__DOT__execute_reg_data[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data[0U] 
@@ -2760,13 +2119,6 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) {
 					      vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data
 					      [0U]), 
 		      VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2));
-    vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__mult_signed_result 
-	= VL_MULS_QQQ(64,64,64, VL_EXTENDS_QI(64,32, 
-					      vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data
-					      [0U]), 
-		      VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2));
-    vlTOPp->Vortex__DOT__fetch_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid
-	[1U];
     vlTOPp->Vortex__DOT__fetch_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid
 	[0U];
     // ALWAYS at VX_alu.v:47
@@ -2896,181 +2248,16 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) {
 						 (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data
 						  [0U] 
 						  + vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2))))));
-    // ALWAYS at VX_alu.v:47
-    vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_alu__out_alu_result 
-	= ((0x10U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-	    ? ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-	        ? 0U : ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-			 ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-			     ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-				 ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)
-				     ? vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data
-				    [0U] : VL_MODDIV_III(32, 
-							 vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data
-							 [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2))
-				 : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)
-				     ? vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data
-				    [0U] : VL_MODDIVS_III(32, 
-							  vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data
-							  [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)))
-			     : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-				 ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)
-				     ? 0xffffffffU : 
-				    VL_DIV_III(32, 
-					       vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data
-					       [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2))
-				 : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)
-				     ? 0xffffffffU : 
-				    VL_DIVS_III(32, 
-						vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data
-						[0U], vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2))))
-			 : ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-			     ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-				 ? (IData)((((QData)((IData)(
-							     vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data
-							     [0U])) 
-					     * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2))) 
-					    >> 0x20U))
-				 : (IData)((((((QData)((IData)(
-							       VL_NEGATE_I((IData)(
-										(1U 
-										& (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data
-										[0U] 
-										>> 0x1fU)))))) 
-					       << 0x20U) 
-					      | (QData)((IData)(
-								vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data
-								[0U]))) 
-					     * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2))) 
-					    >> 0x20U)))
-			     : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-				 ? (IData)((vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__mult_signed_result 
-					    >> 0x20U))
-				 : (IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__mult_signed_result)))))
-	    : ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-	        ? ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-		    ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-		        ? vlTOPp->Vortex__DOT__csr_decode_csr_data
-		        : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-			    ? vlTOPp->Vortex__DOT__csr_decode_csr_data
-			    : (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC 
-			       + (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed 
-				  << 0xcU)))) : ((2U 
-						  & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-						  ? 
-						 ((1U 
-						   & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-						   ? 
-						  (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed 
-						   << 0xcU)
-						   : 
-						  ((vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data
-						    [0U] 
-						    >= vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)
-						    ? 0U
-						    : 0xffffffffU))
-						  : 
-						 ((1U 
-						   & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-						   ? 
-						  (vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2 
-						   & vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data
-						   [0U])
-						   : 
-						  (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data
-						   [0U] 
-						   | vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2))))
-	        : ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-		    ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-		        ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-			    ? VL_SHIFTRS_III(32,32,5, 
-					     vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data
-					     [0U], 
-					     (0x1fU 
-					      & vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2))
-			    : (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data
-			       [0U] >> (0x1fU & vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)))
-		        : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-			    ? (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data
-			       [0U] ^ vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)
-			    : ((vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data
-				[0U] < vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)
-			        ? 1U : 0U))) : ((2U 
-						 & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-						 ? 
-						((1U 
-						  & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-						  ? 
-						 (VL_LTS_III(1,32,32, 
-							     vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data
-							     [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)
-						   ? 1U
-						   : 0U)
-						  : 
-						 (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data
-						  [0U] 
-						  << 
-						  (0x1fU 
-						   & vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)))
-						 : 
-						((1U 
-						  & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op))
-						  ? 
-						 (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data
-						  [0U] 
-						  - vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)
-						  : 
-						 (vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data
-						  [0U] 
-						  + vlTOPp->Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2))))));
-    vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[1U] 
-	= vlTOPp->Vortex__DOT__fetch_valid[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[0U] 
 	= vlTOPp->Vortex__DOT__fetch_valid[0U];
     vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result[0U] 
 	= vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_alu__out_alu_result;
-    vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result[0U] 
-	= vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_alu__out_alu_result;
-    vlTOPp->Vortex__DOT__execute_alu_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result
-	[1U];
     vlTOPp->Vortex__DOT__execute_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result
 	[0U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[1U] 
-	= vlTOPp->Vortex__DOT__execute_alu_result[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[0U] 
 	= vlTOPp->Vortex__DOT__execute_alu_result[0U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[1U] 
-	= vlTOPp->Vortex__DOT__execute_alu_result[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[0U] 
 	= vlTOPp->Vortex__DOT__execute_alu_result[0U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[1U] 
-	= ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd)
-	    ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))
-	        ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next
-	       [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result
-	       [1U]) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd)
-			 ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb))
-			     ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next
-			    [1U] : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb))
-				     ? vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data
-				    [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result
-				    [1U])) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd)
-					       ? ((3U 
-						   == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
-						   ? 
-						  vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next
-						  [1U]
-						   : 
-						  ((2U 
-						    == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
-						    ? 
-						   vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data
-						   [1U]
-						    : 
-						   vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result
-						   [1U]))
-					       : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result
-					      [1U])));
     vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[0U] 
 	= ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd)
 	    ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))
@@ -3099,34 +2286,6 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) {
 						   [0U]))
 					       : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result
 					      [0U])));
-    vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[1U] 
-	= ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd)
-	    ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))
-	        ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next
-	       [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result
-	       [1U]) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd)
-			 ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb))
-			     ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next
-			    [1U] : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb))
-				     ? vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data
-				    [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result
-				    [1U])) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd)
-					       ? ((3U 
-						   == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
-						   ? 
-						  vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next
-						  [1U]
-						   : 
-						  ((2U 
-						    == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
-						    ? 
-						   vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data
-						   [1U]
-						    : 
-						   vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result
-						   [1U]))
-					       : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result
-					      [1U])));
     vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[0U] 
 	= ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd)
 	    ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))
@@ -3155,66 +2314,38 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) {
 						   [0U]))
 					       : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result
 					      [0U])));
-    vlTOPp->Vortex__DOT__forwarding_src2_fwd_data[1U] 
-	= vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data
-	[1U];
     vlTOPp->Vortex__DOT__forwarding_src2_fwd_data[0U] 
 	= vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data
 	[0U];
-    vlTOPp->Vortex__DOT__forwarding_src1_fwd_data[1U] 
-	= vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data
-	[1U];
     vlTOPp->Vortex__DOT__forwarding_src1_fwd_data[0U] 
 	= vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data
 	[0U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[1U] 
-	= vlTOPp->Vortex__DOT__forwarding_src2_fwd_data
-	[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[0U] 
 	= vlTOPp->Vortex__DOT__forwarding_src2_fwd_data
 	[0U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[1U] 
-	= vlTOPp->Vortex__DOT__forwarding_src1_fwd_data
-	[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[0U] 
 	= vlTOPp->Vortex__DOT__forwarding_src1_fwd_data
 	[0U];
     vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data[1U] 
-	= ((IData)(vlTOPp->Vortex__DOT__forwarding_src2_fwd)
+	= ((((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd) 
+	     | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd)) 
+	    | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd))
 	    ? vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data
 	   [0U] : vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register
 	   [0U]);
-    vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data[2U] 
-	= ((IData)(vlTOPp->Vortex__DOT__forwarding_src2_fwd)
-	    ? vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data
-	   [1U] : vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register
-	   [1U]);
     vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data[0U] 
 	= ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))
 	    ? vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC
-	    : ((IData)(vlTOPp->Vortex__DOT__forwarding_src1_fwd)
+	    : ((((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd) 
+		 | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd)) 
+		| (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd))
 	        ? vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data
 	       [0U] : vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register
 	       [0U]));
-    vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data[1U] 
-	= ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))
-	    ? vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC
-	    : ((IData)(vlTOPp->Vortex__DOT__forwarding_src1_fwd)
-	        ? vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data
-	       [1U] : vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register
-	       [1U]));
-    vlTOPp->Vortex__DOT__decode_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data
-	[3U];
-    vlTOPp->Vortex__DOT__decode_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data
-	[2U];
     vlTOPp->Vortex__DOT__decode_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data
 	[1U];
     vlTOPp->Vortex__DOT__decode_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data
 	[0U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data[3U] 
-	= vlTOPp->Vortex__DOT__decode_reg_data[3U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data[2U] 
-	= vlTOPp->Vortex__DOT__decode_reg_data[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data[1U] 
 	= vlTOPp->Vortex__DOT__decode_reg_data[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data[0U] 
@@ -3225,34 +2356,6 @@ VL_INLINE_OPT void VVortex::_combo__TOP__9(VVortex__Syms* __restrict vlSymsp) {
     VL_DEBUG_IF(VL_DBG_MSGF("+    VVortex::_combo__TOP__9\n"); );
     VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
     // Body
-    vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[1U] 
-	= ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd)
-	    ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))
-	        ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next
-	       [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result
-	       [1U]) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd)
-			 ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb))
-			     ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next
-			    [1U] : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb))
-				     ? vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data
-				    [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result
-				    [1U])) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd)
-					       ? ((3U 
-						   == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
-						   ? 
-						  vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next
-						  [1U]
-						   : 
-						  ((2U 
-						    == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
-						    ? 
-						   vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data
-						   [1U]
-						    : 
-						   vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result
-						   [1U]))
-					       : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result
-					      [1U])));
     vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[0U] 
 	= ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd)
 	    ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))
@@ -3281,34 +2384,6 @@ VL_INLINE_OPT void VVortex::_combo__TOP__9(VVortex__Syms* __restrict vlSymsp) {
 						   [0U]))
 					       : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result
 					      [0U])));
-    vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[1U] 
-	= ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd)
-	    ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))
-	        ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next
-	       [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result
-	       [1U]) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd)
-			 ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb))
-			     ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next
-			    [1U] : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb))
-				     ? vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data
-				    [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result
-				    [1U])) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd)
-					       ? ((3U 
-						   == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
-						   ? 
-						  vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next
-						  [1U]
-						   : 
-						  ((2U 
-						    == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
-						    ? 
-						   vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data
-						   [1U]
-						    : 
-						   vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result
-						   [1U]))
-					       : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result
-					      [1U])));
     vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[0U] 
 	= ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd)
 	    ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))
@@ -3337,66 +2412,38 @@ VL_INLINE_OPT void VVortex::_combo__TOP__9(VVortex__Syms* __restrict vlSymsp) {
 						   [0U]))
 					       : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result
 					      [0U])));
-    vlTOPp->Vortex__DOT__forwarding_src2_fwd_data[1U] 
-	= vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data
-	[1U];
     vlTOPp->Vortex__DOT__forwarding_src2_fwd_data[0U] 
 	= vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data
 	[0U];
-    vlTOPp->Vortex__DOT__forwarding_src1_fwd_data[1U] 
-	= vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data
-	[1U];
     vlTOPp->Vortex__DOT__forwarding_src1_fwd_data[0U] 
 	= vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data
 	[0U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[1U] 
-	= vlTOPp->Vortex__DOT__forwarding_src2_fwd_data
-	[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[0U] 
 	= vlTOPp->Vortex__DOT__forwarding_src2_fwd_data
 	[0U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[1U] 
-	= vlTOPp->Vortex__DOT__forwarding_src1_fwd_data
-	[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[0U] 
 	= vlTOPp->Vortex__DOT__forwarding_src1_fwd_data
 	[0U];
     vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data[1U] 
-	= ((IData)(vlTOPp->Vortex__DOT__forwarding_src2_fwd)
+	= ((((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd) 
+	     | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd)) 
+	    | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd))
 	    ? vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data
 	   [0U] : vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register
 	   [0U]);
-    vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data[2U] 
-	= ((IData)(vlTOPp->Vortex__DOT__forwarding_src2_fwd)
-	    ? vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data
-	   [1U] : vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register
-	   [1U]);
     vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data[0U] 
 	= ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))
 	    ? vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC
-	    : ((IData)(vlTOPp->Vortex__DOT__forwarding_src1_fwd)
+	    : ((((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd) 
+		 | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd)) 
+		| (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd))
 	        ? vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data
 	       [0U] : vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register
 	       [0U]));
-    vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data[1U] 
-	= ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))
-	    ? vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC
-	    : ((IData)(vlTOPp->Vortex__DOT__forwarding_src1_fwd)
-	        ? vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data
-	       [1U] : vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register
-	       [1U]));
-    vlTOPp->Vortex__DOT__decode_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data
-	[3U];
-    vlTOPp->Vortex__DOT__decode_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data
-	[2U];
     vlTOPp->Vortex__DOT__decode_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data
 	[1U];
     vlTOPp->Vortex__DOT__decode_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_reg_data
 	[0U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data[3U] 
-	= vlTOPp->Vortex__DOT__decode_reg_data[3U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data[2U] 
-	= vlTOPp->Vortex__DOT__decode_reg_data[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data[1U] 
 	= vlTOPp->Vortex__DOT__decode_reg_data[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data[0U] 
@@ -3478,248 +2525,246 @@ void VVortex::_ctor_var_reset() {
     clk = VL_RAND_RESET_I(1);
     reset = VL_RAND_RESET_I(1);
     fe_instruction = VL_RAND_RESET_I(32);
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    in_cache_driver_out_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
     curr_PC = VL_RAND_RESET_I(32);
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    out_cache_driver_in_address[__Vi0] = VL_RAND_RESET_I(32);
     }}
     out_cache_driver_in_mem_read = VL_RAND_RESET_I(3);
     out_cache_driver_in_mem_write = VL_RAND_RESET_I(3);
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    out_cache_driver_in_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    out_cache_driver_in_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT__fetch_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT__f_d_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
     Vortex__DOT__decode_csr_address = VL_RAND_RESET_I(12);
-    { int __Vi0=0; for (; __Vi0<4; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
 	    Vortex__DOT__decode_reg_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
     Vortex__DOT__decode_itype_immed = VL_RAND_RESET_I(32);
     Vortex__DOT__decode_branch_type = VL_RAND_RESET_I(3);
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT__decode_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<4; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
 	    Vortex__DOT__d_e_reg_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT__d_e_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
     Vortex__DOT__execute_branch_stall = VL_RAND_RESET_I(1);
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT__execute_alu_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<4; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
 	    Vortex__DOT__execute_reg_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT__execute_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT__e_m_alu_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<4; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
 	    Vortex__DOT__e_m_reg_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT__e_m_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
     Vortex__DOT__memory_branch_dir = VL_RAND_RESET_I(1);
     Vortex__DOT__memory_branch_dest = VL_RAND_RESET_I(32);
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT__memory_alu_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT__memory_mem_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT__memory_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT__m_w_alu_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT__m_w_mem_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT__m_w_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT__writeback_write_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
     Vortex__DOT__csr_decode_csr_data = VL_RAND_RESET_I(32);
     Vortex__DOT__forwarding_fwd_stall = VL_RAND_RESET_I(1);
-    Vortex__DOT__forwarding_src1_fwd = VL_RAND_RESET_I(1);
-    Vortex__DOT__forwarding_src2_fwd = VL_RAND_RESET_I(1);
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT__forwarding_src1_fwd_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT__forwarding_src2_fwd_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT____Vcellout__vx_fetch__out_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT____Vcellout__vx_decode__out_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<4; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
 	    Vortex__DOT____Vcellout__vx_decode__out_reg_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_decode__in_write_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_decode__in_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<4; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
 	    Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<4; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT____Vcellout__vx_execute__out_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<4; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
 	    Vortex__DOT____Vcellout__vx_execute__out_reg_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT____Vcellout__vx_execute__out_alu_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_execute__in_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<4; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_execute__in_reg_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<4; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
 	    Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<4; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT__use_rd2[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT____Vcellout__vx_memory__out_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT____Vcellout__vx_memory__out_mem_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT____Vcellout__vx_memory__out_alu_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_memory__in_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_memory__in_rd2[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_memory__in_alu_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT____Vcellout__vx_writeback__out_write_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
     Vortex__DOT__vx_fetch__DOT__stall_reg = VL_RAND_RESET_I(1);
@@ -3733,16 +2778,16 @@ void VVortex::_ctor_var_reset() {
     Vortex__DOT__vx_fetch__DOT__PC_to_use = VL_RAND_RESET_I(32);
     Vortex__DOT__vx_fetch__DOT__stall = VL_RAND_RESET_I(1);
     Vortex__DOT__vx_fetch__DOT__temp_PC = VL_RAND_RESET_I(32);
-    Vortex__DOT__vx_fetch__DOT__valid = VL_RAND_RESET_I(2);
+    Vortex__DOT__vx_fetch__DOT__valid = VL_RAND_RESET_I(1);
     Vortex__DOT__vx_f_d_reg__DOT__instruction = VL_RAND_RESET_I(32);
     Vortex__DOT__vx_f_d_reg__DOT__curr_PC = VL_RAND_RESET_I(32);
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT__vx_f_d_reg__DOT__valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT__vx_decode__DOT__rd1_register[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT__vx_decode__DOT__rd2_register[__Vi0] = VL_RAND_RESET_I(32);
     }}
     Vortex__DOT__vx_decode__DOT__is_itype = VL_RAND_RESET_I(1);
@@ -3752,16 +2797,11 @@ void VVortex::_ctor_var_reset() {
     Vortex__DOT__vx_decode__DOT__temp_final_alu = VL_RAND_RESET_I(5);
     Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_register_file__out_src2_data = VL_RAND_RESET_I(32);
     Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_register_file__out_src1_data = VL_RAND_RESET_I(32);
-    Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file__out_src2_data = VL_RAND_RESET_I(32);
-    Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file__out_src1_data = VL_RAND_RESET_I(32);
     { int __Vi0=0; for (; __Vi0<32; ++__Vi0) {
 	    Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<32; ++__Vi0) {
-	    Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers[__Vi0] = VL_RAND_RESET_I(32);
-    }}
     Vortex__DOT__vx_d_e_reg__DOT__rd = VL_RAND_RESET_I(5);
-    { int __Vi0=0; for (; __Vi0<4; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
 	    Vortex__DOT__vx_d_e_reg__DOT__reg_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
     Vortex__DOT__vx_d_e_reg__DOT__alu_op = VL_RAND_RESET_I(5);
@@ -3779,13 +2819,13 @@ void VVortex::_ctor_var_reset() {
     Vortex__DOT__vx_d_e_reg__DOT__curr_PC = VL_RAND_RESET_I(32);
     Vortex__DOT__vx_d_e_reg__DOT__jal = VL_RAND_RESET_I(1);
     Vortex__DOT__vx_d_e_reg__DOT__jal_offset = VL_RAND_RESET_I(32);
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT__vx_d_e_reg__DOT__valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<4; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
 	    Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT__vx_d_e_reg__DOT__valid_z[__Vi0] = VL_RAND_RESET_I(1);
     }}
     Vortex__DOT__vx_d_e_reg__DOT__stalling = VL_RAND_RESET_I(1);
@@ -3793,19 +2833,13 @@ void VVortex::_ctor_var_reset() {
     { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
 	    Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    Vortex__DOT__vx_execute__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_alu__out_alu_result = VL_RAND_RESET_I(32);
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
-	    Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data[__Vi0] = VL_RAND_RESET_I(32);
-    }}
     Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2 = VL_RAND_RESET_I(32);
     Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__mult_signed_result = VL_RAND_RESET_Q(64);
-    Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2 = VL_RAND_RESET_I(32);
-    Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__mult_signed_result = VL_RAND_RESET_Q(64);
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT__vx_e_m_reg__DOT__alu_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
     Vortex__DOT__vx_e_m_reg__DOT__rd = VL_RAND_RESET_I(5);
-    { int __Vi0=0; for (; __Vi0<4; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
 	    Vortex__DOT__vx_e_m_reg__DOT__reg_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
     Vortex__DOT__vx_e_m_reg__DOT__wb = VL_RAND_RESET_I(2);
@@ -3820,22 +2854,22 @@ void VVortex::_ctor_var_reset() {
     Vortex__DOT__vx_e_m_reg__DOT__branch_type = VL_RAND_RESET_I(3);
     Vortex__DOT__vx_e_m_reg__DOT__jal = VL_RAND_RESET_I(1);
     Vortex__DOT__vx_e_m_reg__DOT__jal_dest = VL_RAND_RESET_I(32);
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT__vx_e_m_reg__DOT__valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT__vx_m_w_reg__DOT__alu_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT__vx_m_w_reg__DOT__mem_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
     Vortex__DOT__vx_m_w_reg__DOT__rd = VL_RAND_RESET_I(5);
     Vortex__DOT__vx_m_w_reg__DOT__wb = VL_RAND_RESET_I(2);
     Vortex__DOT__vx_m_w_reg__DOT__PC_next = VL_RAND_RESET_I(32);
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT__vx_m_w_reg__DOT__valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT__vx_writeback__DOT__out_pc_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
     Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd = VL_RAND_RESET_I(1);
@@ -3844,13 +2878,13 @@ void VVortex::_ctor_var_reset() {
     Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd = VL_RAND_RESET_I(1);
     Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd = VL_RAND_RESET_I(1);
     Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd = VL_RAND_RESET_I(1);
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<1; ++__Vi0) {
 	    Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[__Vi0] = VL_RAND_RESET_I(32);
     }}
     { int __Vi0=0; for (; __Vi0<4096; ++__Vi0) {
diff --git a/rtl/obj_dir/VVortex.h b/rtl/obj_dir/VVortex.h
index 007ba2a8..1bcc6c56 100644
--- a/rtl/obj_dir/VVortex.h
+++ b/rtl/obj_dir/VVortex.h
@@ -8,7 +8,7 @@
 #ifndef _VVortex_H_
 #define _VVortex_H_
 
-#include "verilated.h"
+#include "verilated_heavy.h"
 
 class VVortex__Syms;
 
@@ -27,10 +27,10 @@ VL_MODULE(VVortex) {
     VL_OUT8(out_cache_driver_in_mem_write,2,0);
     VL_IN(fe_instruction,31,0);
     VL_OUT(curr_PC,31,0);
-    VL_IN(in_cache_driver_out_data[2],31,0);
-    VL_OUT(out_cache_driver_in_address[2],31,0);
-    VL_OUT8(out_cache_driver_in_valid[2],0,0);
-    VL_OUT(out_cache_driver_in_data[2],31,0);
+    VL_IN(in_cache_driver_out_data[1],31,0);
+    VL_OUT(out_cache_driver_in_address[1],31,0);
+    VL_OUT8(out_cache_driver_in_valid[1],0,0);
+    VL_OUT(out_cache_driver_in_data[1],31,0);
     
     // LOCAL SIGNALS
     // Internals; generally not touched by application code
@@ -41,14 +41,12 @@ VL_MODULE(VVortex) {
 	VL_SIG8(Vortex__DOT__execute_branch_stall,0,0);
 	VL_SIG8(Vortex__DOT__memory_branch_dir,0,0);
 	VL_SIG8(Vortex__DOT__forwarding_fwd_stall,0,0);
-	VL_SIG8(Vortex__DOT__forwarding_src1_fwd,0,0);
-	VL_SIG8(Vortex__DOT__forwarding_src2_fwd,0,0);
 	VL_SIG8(Vortex__DOT__vx_fetch__DOT__stall_reg,0,0);
 	VL_SIG8(Vortex__DOT__vx_fetch__DOT__delay_reg,0,0);
 	VL_SIG8(Vortex__DOT__vx_fetch__DOT__state,4,0);
 	VL_SIG8(Vortex__DOT__vx_fetch__DOT__prev_debug,0,0);
 	VL_SIG8(Vortex__DOT__vx_fetch__DOT__stall,0,0);
-	VL_SIG8(Vortex__DOT__vx_fetch__DOT__valid,1,0);
+	VL_SIG8(Vortex__DOT__vx_fetch__DOT__valid,0,0);
 	VL_SIG8(Vortex__DOT__vx_decode__DOT__is_itype,0,0);
 	VL_SIG8(Vortex__DOT__vx_decode__DOT__is_csr,0,0);
 	VL_SIG8(Vortex__DOT__vx_decode__DOT__mul_alu,4,0);
@@ -101,60 +99,57 @@ VL_MODULE(VVortex) {
 	VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__curr_PC,31,0);
 	VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__jal_offset,31,0);
 	VL_SIG(Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
-    };
-    struct {
-	VL_SIG(Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
 	VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__PC_next,31,0);
 	VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__csr_result,31,0);
+    };
+    struct {
 	VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__curr_PC,31,0);
 	VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__branch_offset,31,0);
 	VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__jal_dest,31,0);
 	VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__PC_next,31,0);
 	VL_SIG64(Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__mult_signed_result,63,0);
-	VL_SIG64(Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__mult_signed_result,63,0);
 	VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__cycle,63,0);
 	VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__instret,63,0);
-	VL_SIG8(Vortex__DOT__fetch_valid[2],0,0);
-	VL_SIG8(Vortex__DOT__f_d_valid[2],0,0);
-	VL_SIG(Vortex__DOT__decode_reg_data[4],31,0);
-	VL_SIG8(Vortex__DOT__decode_valid[2],0,0);
-	VL_SIG(Vortex__DOT__d_e_reg_data[4],31,0);
-	VL_SIG8(Vortex__DOT__d_e_valid[2],0,0);
-	VL_SIG(Vortex__DOT__execute_alu_result[2],31,0);
-	VL_SIG(Vortex__DOT__execute_reg_data[4],31,0);
-	VL_SIG8(Vortex__DOT__execute_valid[2],0,0);
-	VL_SIG(Vortex__DOT__e_m_alu_result[2],31,0);
-	VL_SIG(Vortex__DOT__e_m_reg_data[4],31,0);
-	VL_SIG8(Vortex__DOT__e_m_valid[2],0,0);
-	VL_SIG(Vortex__DOT__memory_alu_result[2],31,0);
-	VL_SIG(Vortex__DOT__memory_mem_result[2],31,0);
-	VL_SIG8(Vortex__DOT__memory_valid[2],0,0);
-	VL_SIG(Vortex__DOT__m_w_alu_result[2],31,0);
-	VL_SIG(Vortex__DOT__m_w_mem_result[2],31,0);
-	VL_SIG8(Vortex__DOT__m_w_valid[2],0,0);
-	VL_SIG(Vortex__DOT__writeback_write_data[2],31,0);
-	VL_SIG(Vortex__DOT__forwarding_src1_fwd_data[2],31,0);
-	VL_SIG(Vortex__DOT__forwarding_src2_fwd_data[2],31,0);
-	VL_SIG(Vortex__DOT__use_rd2[2],31,0);
-	VL_SIG8(Vortex__DOT__vx_f_d_reg__DOT__valid[2],0,0);
-	VL_SIG(Vortex__DOT__vx_decode__DOT__rd1_register[2],31,0);
-	VL_SIG(Vortex__DOT__vx_decode__DOT__rd2_register[2],31,0);
+	VL_SIG8(Vortex__DOT__fetch_valid[1],0,0);
+	VL_SIG8(Vortex__DOT__f_d_valid[1],0,0);
+	VL_SIG(Vortex__DOT__decode_reg_data[2],31,0);
+	VL_SIG8(Vortex__DOT__decode_valid[1],0,0);
+	VL_SIG(Vortex__DOT__d_e_reg_data[2],31,0);
+	VL_SIG8(Vortex__DOT__d_e_valid[1],0,0);
+	VL_SIG(Vortex__DOT__execute_alu_result[1],31,0);
+	VL_SIG(Vortex__DOT__execute_reg_data[2],31,0);
+	VL_SIG8(Vortex__DOT__execute_valid[1],0,0);
+	VL_SIG(Vortex__DOT__e_m_alu_result[1],31,0);
+	VL_SIG(Vortex__DOT__e_m_reg_data[2],31,0);
+	VL_SIG8(Vortex__DOT__e_m_valid[1],0,0);
+	VL_SIG(Vortex__DOT__memory_alu_result[1],31,0);
+	VL_SIG(Vortex__DOT__memory_mem_result[1],31,0);
+	VL_SIG8(Vortex__DOT__memory_valid[1],0,0);
+	VL_SIG(Vortex__DOT__m_w_alu_result[1],31,0);
+	VL_SIG(Vortex__DOT__m_w_mem_result[1],31,0);
+	VL_SIG8(Vortex__DOT__m_w_valid[1],0,0);
+	VL_SIG(Vortex__DOT__writeback_write_data[1],31,0);
+	VL_SIG(Vortex__DOT__forwarding_src1_fwd_data[1],31,0);
+	VL_SIG(Vortex__DOT__forwarding_src2_fwd_data[1],31,0);
+	VL_SIG(Vortex__DOT__use_rd2[1],31,0);
+	VL_SIG8(Vortex__DOT__vx_f_d_reg__DOT__valid[1],0,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT__rd1_register[1],31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT__rd2_register[1],31,0);
 	VL_SIG(Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers[32],31,0);
-	VL_SIG(Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers[32],31,0);
-	VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__reg_data[4],31,0);
-	VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid[2],0,0);
-	VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[4],31,0);
-	VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid_z[2],0,0);
-	VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__alu_result[2],31,0);
-	VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__reg_data[4],31,0);
-	VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__valid[2],0,0);
-	VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__alu_result[2],31,0);
-	VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__mem_result[2],31,0);
-	VL_SIG8(Vortex__DOT__vx_m_w_reg__DOT__valid[2],0,0);
-	VL_SIG(Vortex__DOT__vx_writeback__DOT__out_pc_data[2],31,0);
-	VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[2],31,0);
-	VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[2],31,0);
-	VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[2],31,0);
+	VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__reg_data[2],31,0);
+	VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid[1],0,0);
+	VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[2],31,0);
+	VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid_z[1],0,0);
+	VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__alu_result[1],31,0);
+	VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__reg_data[2],31,0);
+	VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__valid[1],0,0);
+	VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__alu_result[1],31,0);
+	VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__mem_result[1],31,0);
+	VL_SIG8(Vortex__DOT__vx_m_w_reg__DOT__valid[1],0,0);
+	VL_SIG(Vortex__DOT__vx_writeback__DOT__out_pc_data[1],31,0);
+	VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[1],31,0);
+	VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[1],31,0);
+	VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[1],31,0);
 	VL_SIG16(Vortex__DOT__vx_csr_handler__DOT__csr[4096],11,0);
     };
     
@@ -166,63 +161,59 @@ VL_MODULE(VVortex) {
     VL_SIG8(__Vclklast__TOP__reset,0,0);
     VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_register_file__out_src2_data,31,0);
     VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_register_file__out_src1_data,31,0);
-    VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file__out_src2_data,31,0);
-    VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file__out_src1_data,31,0);
     VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_alu__out_alu_result,31,0);
-    VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_alu__out_alu_result,31,0);
-    VL_SIG8(Vortex__DOT____Vcellout__vx_fetch__out_valid[2],0,0);
-    VL_SIG8(Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[2],0,0);
-    VL_SIG8(Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[2],0,0);
-    VL_SIG8(Vortex__DOT____Vcellout__vx_decode__out_valid[2],0,0);
-    VL_SIG(Vortex__DOT____Vcellout__vx_decode__out_reg_data[4],31,0);
-    VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[2],31,0);
-    VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[2],31,0);
-    VL_SIG8(Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[2],0,0);
-    VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_write_data[2],31,0);
-    VL_SIG8(Vortex__DOT____Vcellinp__vx_decode__in_valid[2],0,0);
-    VL_SIG8(Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[2],0,0);
-    VL_SIG(Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data[4],31,0);
-    VL_SIG8(Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[2],0,0);
-    VL_SIG(Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data[4],31,0);
-    VL_SIG8(Vortex__DOT____Vcellout__vx_execute__out_valid[2],0,0);
-    VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_reg_data[4],31,0);
-    VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_alu_result[2],31,0);
-    VL_SIG8(Vortex__DOT____Vcellinp__vx_execute__in_valid[2],0,0);
-    VL_SIG(Vortex__DOT____Vcellinp__vx_execute__in_reg_data[4],31,0);
-    VL_SIG8(Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[2],0,0);
-    VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data[4],31,0);
-    VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[2],31,0);
-    VL_SIG8(Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[2],0,0);
-    VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data[4],31,0);
-    VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[2],31,0);
-    VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[2],0,0);
-    VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[2],31,0);
-    VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[2],31,0);
-    VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_valid[2],0,0);
-    VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_mem_result[2],31,0);
-    VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_alu_result[2],31,0);
-    VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[2],31,0);
-    VL_SIG8(Vortex__DOT____Vcellinp__vx_memory__in_valid[2],0,0);
-    VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_rd2[2],31,0);
-    VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_alu_result[2],31,0);
-    VL_SIG8(Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[2],0,0);
-    VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[2],31,0);
-    VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[2],31,0);
-    VL_SIG8(Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[2],0,0);
-    VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[2],31,0);
-    VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[2],31,0);
-    VL_SIG(Vortex__DOT____Vcellout__vx_writeback__out_write_data[2],31,0);
-    VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[2],31,0);
-    VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[2],31,0);
-    VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[2],31,0);
-    VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[2],31,0);
-    VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[2],31,0);
-    VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[2],31,0);
-    VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[2],31,0);
-    VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[2],31,0);
-    VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[2],31,0);
+    VL_SIG8(Vortex__DOT____Vcellout__vx_fetch__out_valid[1],0,0);
+    VL_SIG8(Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[1],0,0);
+    VL_SIG8(Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[1],0,0);
+    VL_SIG8(Vortex__DOT____Vcellout__vx_decode__out_valid[1],0,0);
+    VL_SIG(Vortex__DOT____Vcellout__vx_decode__out_reg_data[2],31,0);
+    VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[1],31,0);
+    VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[1],31,0);
+    VL_SIG8(Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[1],0,0);
+    VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_write_data[1],31,0);
+    VL_SIG8(Vortex__DOT____Vcellinp__vx_decode__in_valid[1],0,0);
+    VL_SIG8(Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[1],0,0);
+    VL_SIG(Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data[2],31,0);
+    VL_SIG8(Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[1],0,0);
+    VL_SIG(Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data[2],31,0);
+    VL_SIG8(Vortex__DOT____Vcellout__vx_execute__out_valid[1],0,0);
+    VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_reg_data[2],31,0);
+    VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_alu_result[1],31,0);
+    VL_SIG8(Vortex__DOT____Vcellinp__vx_execute__in_valid[1],0,0);
+    VL_SIG(Vortex__DOT____Vcellinp__vx_execute__in_reg_data[2],31,0);
+    VL_SIG8(Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[1],0,0);
+    VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data[2],31,0);
+    VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[1],31,0);
+    VL_SIG8(Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[1],0,0);
+    VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data[2],31,0);
+    VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[1],31,0);
+    VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[1],0,0);
+    VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[1],31,0);
+    VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[1],31,0);
+    VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_valid[1],0,0);
+    VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_mem_result[1],31,0);
+    VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_alu_result[1],31,0);
+    VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[1],31,0);
+    VL_SIG8(Vortex__DOT____Vcellinp__vx_memory__in_valid[1],0,0);
+    VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_rd2[1],31,0);
+    VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_alu_result[1],31,0);
+    VL_SIG8(Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[1],0,0);
+    VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[1],31,0);
+    VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[1],31,0);
+    VL_SIG8(Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[1],0,0);
+    VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[1],31,0);
+    VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[1],31,0);
+    VL_SIG(Vortex__DOT____Vcellout__vx_writeback__out_write_data[1],31,0);
+    VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[1],31,0);
+    VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[1],31,0);
+    VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[1],31,0);
+    VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[1],31,0);
+    VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[1],31,0);
+    VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[1],31,0);
+    VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[1],31,0);
+    VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[1],31,0);
+    VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[1],31,0);
     VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data[2],31,0);
-    VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data[2],31,0);
     static VL_ST_SIG8(__Vtable1_Vortex__DOT__vx_decode__DOT__mul_alu[8],4,0);
     
     // INTERNAL VARIABLES
diff --git a/rtl/obj_dir/VVortex.mk b/rtl/obj_dir/VVortex.mk
index edc5fcca..eedf8cab 100644
--- a/rtl/obj_dir/VVortex.mk
+++ b/rtl/obj_dir/VVortex.mk
@@ -10,7 +10,7 @@ default: VVortex
 # Perl executable (from $PERL)
 PERL = perl
 # Path to Verilator kit (from $VERILATOR_ROOT)
-VERILATOR_ROOT = /usr/local/Cellar/verilator/4.010/share/verilator
+VERILATOR_ROOT = /usr/local/share/verilator
 # SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE)
 SYSTEMC_INCLUDE ?= 
 # SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR)
diff --git a/rtl/obj_dir/VVortex__ALL.a b/rtl/obj_dir/VVortex__ALL.a
index 06200527..6c0efc5a 100644
Binary files a/rtl/obj_dir/VVortex__ALL.a and b/rtl/obj_dir/VVortex__ALL.a differ
diff --git a/rtl/obj_dir/VVortex__ALLcls.d b/rtl/obj_dir/VVortex__ALLcls.d
index 1e080335..18515f59 100644
--- a/rtl/obj_dir/VVortex__ALLcls.d
+++ b/rtl/obj_dir/VVortex__ALLcls.d
@@ -1,4 +1,4 @@
 VVortex__ALLcls.o: VVortex__ALLcls.cpp VVortex.cpp VVortex.h \
-  /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.h \
-  /usr/local/Cellar/verilator/4.010/share/verilator/include/verilatedos.h \
-  VVortex__Syms.h
+ /usr/local/share/verilator/include/verilated_heavy.h \
+ /usr/local/share/verilator/include/verilated.h \
+ /usr/local/share/verilator/include/verilatedos.h VVortex__Syms.h
diff --git a/rtl/obj_dir/VVortex__ALLcls.o b/rtl/obj_dir/VVortex__ALLcls.o
index 2b7dbaf8..34c6ebeb 100644
Binary files a/rtl/obj_dir/VVortex__ALLcls.o and b/rtl/obj_dir/VVortex__ALLcls.o differ
diff --git a/rtl/obj_dir/VVortex__ALLsup.d b/rtl/obj_dir/VVortex__ALLsup.d
index 41db4492..9a632abb 100644
--- a/rtl/obj_dir/VVortex__ALLsup.d
+++ b/rtl/obj_dir/VVortex__ALLsup.d
@@ -1,4 +1,4 @@
 VVortex__ALLsup.o: VVortex__ALLsup.cpp VVortex__Syms.cpp VVortex__Syms.h \
-  /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.h \
-  /usr/local/Cellar/verilator/4.010/share/verilator/include/verilatedos.h \
-  VVortex.h
+ /usr/local/share/verilator/include/verilated_heavy.h \
+ /usr/local/share/verilator/include/verilated.h \
+ /usr/local/share/verilator/include/verilatedos.h VVortex.h
diff --git a/rtl/obj_dir/VVortex__ALLsup.o b/rtl/obj_dir/VVortex__ALLsup.o
index 646b75f2..5a0f100d 100644
Binary files a/rtl/obj_dir/VVortex__ALLsup.o and b/rtl/obj_dir/VVortex__ALLsup.o differ
diff --git a/rtl/obj_dir/VVortex__Syms.h b/rtl/obj_dir/VVortex__Syms.h
index bf4ad048..e3fe9800 100644
--- a/rtl/obj_dir/VVortex__Syms.h
+++ b/rtl/obj_dir/VVortex__Syms.h
@@ -6,7 +6,7 @@
 #ifndef _VVortex__Syms_H_
 #define _VVortex__Syms_H_
 
-#include "verilated.h"
+#include "verilated_heavy.h"
 
 // INCLUDE MODULE CLASSES
 #include "VVortex.h"
diff --git a/rtl/obj_dir/VVortex__ver.d b/rtl/obj_dir/VVortex__ver.d
index 7c599475..e8d44c41 100644
--- a/rtl/obj_dir/VVortex__ver.d
+++ b/rtl/obj_dir/VVortex__ver.d
@@ -1 +1 @@
-obj_dir/VVortex.cpp obj_dir/VVortex.h obj_dir/VVortex.mk obj_dir/VVortex__Syms.cpp obj_dir/VVortex__Syms.h obj_dir/VVortex__ver.d obj_dir/VVortex_classes.mk  : /usr/local/Cellar/verilator/4.010/bin/verilator_bin   /usr/local/Cellar/verilator/4.010/bin/verilator_bin VX_alu.v VX_csr_handler.v VX_d_e_reg.v VX_decode.v VX_define.v VX_e_m_reg.v VX_execute.v VX_f_d_reg.v VX_fetch.v VX_forwarding.v VX_m_w_reg.v VX_memory.v VX_register_file.v VX_writeback.v Vortex.v 
+obj_dir/VVortex.cpp obj_dir/VVortex.h obj_dir/VVortex.mk obj_dir/VVortex__Syms.cpp obj_dir/VVortex__Syms.h obj_dir/VVortex__ver.d obj_dir/VVortex_classes.mk  : /usr/local/bin/verilator_bin   /usr/local/bin/verilator_bin VX_alu.v VX_csr_handler.v VX_d_e_reg.v VX_decode.v VX_define.v VX_e_m_reg.v VX_execute.v VX_f_d_reg.v VX_fetch.v VX_forwarding.v VX_m_w_reg.v VX_memory.v VX_register_file.v VX_writeback.v Vortex.v 
diff --git a/rtl/obj_dir/VVortex__verFiles.dat b/rtl/obj_dir/VVortex__verFiles.dat
index a8cb3a3c..d6ce8860 100644
--- a/rtl/obj_dir/VVortex__verFiles.dat
+++ b/rtl/obj_dir/VVortex__verFiles.dat
@@ -1,26 +1,26 @@
 # DESCRIPTION: Verilator output: Timestamp data for --skip-identical.  Delete at will.
 C "-Wall -cc Vortex.v VX_alu.v VX_fetch.v VX_f_d_reg.v VX_decode.v VX_register_file.v VX_d_e_reg.v VX_execute.v VX_e_m_reg.v VX_memory.v VX_m_w_reg.v VX_writeback.v VX_csr_handler.v VX_forwarding.v --exe test_bench.cpp"
-S   4608404 12889046060  1553037052           0  1548678579           0 "/usr/local/Cellar/verilator/4.010/bin/verilator_bin"
-S      2782 12889318286  1553669148           0  1553669148           0 "VX_alu.v"
-S      1495 12889087229  1553211178           0  1553211178           0 "VX_csr_handler.v"
-S      4780 12889318287  1553672988           0  1553672988           0 "VX_d_e_reg.v"
-S     10713 12889318288  1553673019           0  1553673019           0 "VX_decode.v"
-S      1551 12889079483  1553661565           0  1553661565           0 "VX_define.v"
-S      3941 12889318289  1553673060           0  1553673060           0 "VX_e_m_reg.v"
-S      3370 12889318290  1553673095           0  1553673095           0 "VX_execute.v"
-S      1382 12889050060  1553673124           0  1553673124           0 "VX_f_d_reg.v"
-S      3941 12889047675  1553673132           0  1553673132           0 "VX_fetch.v"
-S      5632 12889086478  1553672336           0  1553672336           0 "VX_forwarding.v"
-S      1677 12889085814  1553673165           0  1553673165           0 "VX_m_w_reg.v"
-S      2790 12889084513  1553673201           0  1553673201           0 "VX_memory.v"
-S      1000 12889070228  1553659195           0  1553659195           0 "VX_register_file.v"
-S      1010 12889086287  1553671609           0  1553671609           0 "VX_writeback.v"
-S     15611 12889318291  1553672889           0  1553672889           0 "Vortex.v"
-T    190167 12889376837  1553673213           0  1553673213           0 "obj_dir/VVortex.cpp"
-T     14844 12889376836  1553673213           0  1553673213           0 "obj_dir/VVortex.h"
-T      1800 12889376839  1553673213           0  1553673213           0 "obj_dir/VVortex.mk"
-T       530 12889376835  1553673213           0  1553673213           0 "obj_dir/VVortex__Syms.cpp"
-T       711 12889376834  1553673213           0  1553673213           0 "obj_dir/VVortex__Syms.h"
-T       464 12889376840  1553673213           0  1553673213           0 "obj_dir/VVortex__ver.d"
-T         0        0  1553673213           0  1553673213           0 "obj_dir/VVortex__verFiles.dat"
-T      1159 12889376838  1553673213           0  1553673213           0 "obj_dir/VVortex_classes.mk"
+S   5163137   401094  1553636247   412576209  1553636247   412576209 "/usr/local/bin/verilator_bin"
+S      2782  5518365  1553641993   611294425  1553641993   611294425 "VX_alu.v"
+S      1495  5518326  1553635490   361093288  1553635490   361093288 "VX_csr_handler.v"
+S      4780  5518327  1553705050   153020819  1553705050   153020819 "VX_d_e_reg.v"
+S     10711  5518328  1553706261   998510628  1553706261   998510628 "VX_decode.v"
+S      1551  5518330  1553706438   435305366  1553706438   435305366 "VX_define.v"
+S      3941  5518331  1553705050   153020819  1553705050   153020819 "VX_e_m_reg.v"
+S      3370  5518332  1553705050   153020819  1553705050   153020819 "VX_execute.v"
+S      1382  5518333  1553705050   153020819  1553705050   153020819 "VX_f_d_reg.v"
+S      3944  5518334  1553706489   155533656  1553706489   155533656 "VX_fetch.v"
+S      5632  5518335  1553705050   153020819  1553705050   153020819 "VX_forwarding.v"
+S      1677  5518336  1553705050   153020819  1553705050   153020819 "VX_m_w_reg.v"
+S      2790  5518337  1553705050   153020819  1553705050   153020819 "VX_memory.v"
+S       997  5518338  1553705589   591472686  1553705589   591472686 "VX_register_file.v"
+S       986  5518339  1553706081   977698760  1553706081   977698760 "VX_writeback.v"
+S     15638  5518364  1553706457   931393127  1553706457   931393127 "Vortex.v"
+T    134893  5518343  1553706491   727545232  1553706491   727545232 "obj_dir/VVortex.cpp"
+T     13928  5518342  1553706491   723545213  1553706491   723545213 "obj_dir/VVortex.h"
+T      1777  5518345  1553706491   727545232  1553706491   727545232 "obj_dir/VVortex.mk"
+T       530  5518341  1553706491   723545213  1553706491   723545213 "obj_dir/VVortex__Syms.cpp"
+T       717  5518340  1553706491   723545213  1553706491   723545213 "obj_dir/VVortex__Syms.h"
+T       418  5518346  1553706491   727545232  1553706491   727545232 "obj_dir/VVortex__ver.d"
+T         0        0  1553706491   727545232  1553706491   727545232 "obj_dir/VVortex__verFiles.dat"
+T      1159  5518344  1553706491   727545232  1553706491   727545232 "obj_dir/VVortex_classes.mk"
diff --git a/rtl/obj_dir/debug.txt b/rtl/obj_dir/debug.txt
new file mode 100644
index 00000000..fb95d59e
--- /dev/null
+++ b/rtl/obj_dir/debug.txt
@@ -0,0 +1,2598 @@
+
+
+(0) Inst: ffffffff
+Decode: curr_pc: 00000000
+
+
+(4) Inst: f1401073
+Decode: curr_pc: 00000000
+
+
+(8) Inst: 30101073
+Decode: curr_pc: 00000004
+
+
+(c) Inst: 800000b7
+Decode: curr_pc: 00000008
+
+
+(10) Inst: 80e7
+Decode: curr_pc: 0000000c
+(00000004) WB Data: babebabe, to register:  0
+
+
+(14) Inst: ffffffff
+Decode: curr_pc: 00000010
+(00000008) WB Data: babebabe, to register:  0
+
+
+(14) Inst: ffffffff
+Decode: curr_pc: 00000014
+(0000000c) WB Data: babebabe, to register:  1
+
+
+(80000000) Inst: 4c0006f
+Decode: curr_pc: 00000014
+Writing 80000000 to  1
+(00000010) WB Data: babebabe, to register:  1
+
+
+(80000004) Inst: 34202f73
+Decode: curr_pc: 80000000
+Writing 00000014 to  1
+
+
+(80000004) Inst: 34202f73
+Decode: curr_pc: 80000004
+
+
+(8000004c) Inst: f1402573
+Decode: curr_pc: 80000004
+(80000000) WB Data: babebabe, to register:  0
+
+
+(80000050) Inst: 51063
+Decode: curr_pc: 8000004c
+
+
+(80000054) Inst: 30102573
+Decode: curr_pc: 80000050
+
+
+(80000054) Inst: 30102573
+Decode: curr_pc: 80000054
+(8000004c) WB Data: babebabe, to register: 10
+
+
+(80000054) Inst: 30102573
+Decode: curr_pc: 80000054
+Writing 00000000 to 10
+
+
+(80000058) Inst: 55863
+Decode: curr_pc: 80000054
+
+
+(8000005c) Inst: ff0000f
+Decode: curr_pc: 80000058
+
+
+(8000005c) Inst: ff0000f
+Decode: curr_pc: 8000005c
+(80000054) WB Data: babebabe, to register: 10
+
+
+(80000068) Inst: e13
+Decode: curr_pc: 8000005c
+Writing 00000000 to 10
+
+
+(8000006c) Inst: 297
+Decode: curr_pc: 80000068
+
+
+(80000070) Inst: f9828293
+Decode: curr_pc: 8000006c
+
+
+(80000074) Inst: 30529073
+Decode: curr_pc: 80000070
+(80000068) WB Data: babebabe, to register: 28
+
+
+(80000078) Inst: 30205073
+Decode: curr_pc: 80000074
+Writing 00000000 to 28
+(8000006c) WB Data: babebabe, to register:  5
+
+
+(8000007c) Inst: 30305073
+Decode: curr_pc: 80000078
+Writing 8000006c to  5
+(80000070) WB Data: babebabe, to register:  5
+
+
+(80000080) Inst: 30405073
+Decode: curr_pc: 8000007c
+Writing 80000004 to  5
+(80000074) WB Data: babebabe, to register:  0
+
+
+(80000084) Inst: 80000297
+Decode: curr_pc: 80000080
+(80000078) WB Data: babebabe, to register:  0
+
+
+(80000088) Inst: f7c28293
+Decode: curr_pc: 80000084
+(8000007c) WB Data: babebabe, to register:  0
+
+
+(8000008c) Inst: 28c63
+Decode: curr_pc: 80000088
+(80000080) WB Data: babebabe, to register:  0
+
+
+(80000090) Inst: 10529073
+Decode: curr_pc: 8000008c
+(80000084) WB Data: babebabe, to register:  5
+
+
+(80000090) Inst: 10529073
+Decode: curr_pc: 80000090
+Writing 00000084 to  5
+(80000088) WB Data: babebabe, to register:  5
+
+
+(800000a4) Inst: 30005073
+Decode: curr_pc: 80000090
+Writing 00000000 to  5
+
+
+(800000a8) Inst: 297
+Decode: curr_pc: 800000a4
+
+
+(800000ac) Inst: 1428293
+Decode: curr_pc: 800000a8
+
+
+(800000b0) Inst: 34129073
+Decode: curr_pc: 800000ac
+(800000a4) WB Data: babebabe, to register:  0
+
+
+(800000b4) Inst: f1402573
+Decode: curr_pc: 800000b0
+(800000a8) WB Data: babebabe, to register:  5
+
+
+(800000b8) Inst: 30200073
+Decode: curr_pc: 800000b4
+Writing 800000a8 to  5
+(800000ac) WB Data: babebabe, to register:  5
+
+
+(800000bc) Inst: 93
+Decode: curr_pc: 800000b8
+Writing 800000bc to  5
+(800000b0) WB Data: babebabe, to register:  0
+
+
+(800000c0) Inst: 113
+Decode: curr_pc: 800000bc
+(800000b4) WB Data: babebabe, to register: 10
+
+
+(800000c4) Inst: 402081b3
+Decode: curr_pc: 800000c0
+Writing 00000000 to 10
+(800000b8) WB Data: babebabe, to register:  0
+
+
+(800000c8) Inst: e93
+Decode: curr_pc: 800000c4
+(800000bc) WB Data: babebabe, to register:  1
+
+
+(800000cc) Inst: 200e13
+Decode: curr_pc: 800000c8
+Writing 00000000 to  1
+(800000c0) WB Data: babebabe, to register:  2
+
+
+(800000d0) Inst: 4bd19663
+Decode: curr_pc: 800000cc
+Writing 00000000 to  2
+(800000c4) WB Data: babebabe, to register:  3
+
+
+(800000d4) Inst: 100093
+Decode: curr_pc: 800000d0
+Writing 00000000 to  3
+(800000c8) WB Data: babebabe, to register: 29
+
+
+(800000d4) Inst: 100093
+Decode: curr_pc: 800000d4
+Writing 00000000 to 29
+(800000cc) WB Data: babebabe, to register: 28
+
+
+(800000d4) Inst: 100093
+Decode: curr_pc: 800000d4
+Writing 00000002 to 28
+
+
+(800000d8) Inst: 100113
+Decode: curr_pc: 800000d4
+
+
+(800000dc) Inst: 402081b3
+Decode: curr_pc: 800000d8
+
+
+(800000e0) Inst: e93
+Decode: curr_pc: 800000dc
+(800000d4) WB Data: babebabe, to register:  1
+
+
+(800000e4) Inst: 300e13
+Decode: curr_pc: 800000e0
+Writing 00000001 to  1
+(800000d8) WB Data: babebabe, to register:  2
+
+
+(800000e8) Inst: 49d19a63
+Decode: curr_pc: 800000e4
+Writing 00000001 to  2
+(800000dc) WB Data: babebabe, to register:  3
+
+
+(800000ec) Inst: 300093
+Decode: curr_pc: 800000e8
+Writing 00000000 to  3
+(800000e0) WB Data: babebabe, to register: 29
+
+
+(800000ec) Inst: 300093
+Decode: curr_pc: 800000ec
+Writing 00000000 to 29
+(800000e4) WB Data: babebabe, to register: 28
+
+
+(800000ec) Inst: 300093
+Decode: curr_pc: 800000ec
+Writing 00000003 to 28
+
+
+(800000f0) Inst: 700113
+Decode: curr_pc: 800000ec
+
+
+(800000f4) Inst: 402081b3
+Decode: curr_pc: 800000f0
+
+
+(800000f8) Inst: ffc00e93
+Decode: curr_pc: 800000f4
+(800000ec) WB Data: babebabe, to register:  1
+
+
+(800000fc) Inst: 400e13
+Decode: curr_pc: 800000f8
+Writing 00000003 to  1
+(800000f0) WB Data: babebabe, to register:  2
+
+
+(80000100) Inst: 47d19e63
+Decode: curr_pc: 800000fc
+Writing 00000007 to  2
+(800000f4) WB Data: babebabe, to register:  3
+
+
+(80000104) Inst: 93
+Decode: curr_pc: 80000100
+Writing fffffffc to  3
+(800000f8) WB Data: babebabe, to register: 29
+
+
+(80000104) Inst: 93
+Decode: curr_pc: 80000104
+Writing fffffffc to 29
+(800000fc) WB Data: babebabe, to register: 28
+
+
+(80000104) Inst: 93
+Decode: curr_pc: 80000104
+Writing 00000004 to 28
+
+
+(80000108) Inst: ffff8137
+Decode: curr_pc: 80000104
+
+
+(8000010c) Inst: 402081b3
+Decode: curr_pc: 80000108
+
+
+(80000110) Inst: 8eb7
+Decode: curr_pc: 8000010c
+(80000104) WB Data: babebabe, to register:  1
+
+
+(80000114) Inst: 500e13
+Decode: curr_pc: 80000110
+Writing 00000000 to  1
+(80000108) WB Data: babebabe, to register:  2
+
+
+(80000118) Inst: 47d19263
+Decode: curr_pc: 80000114
+Writing ffff8000 to  2
+(8000010c) WB Data: babebabe, to register:  3
+
+
+(8000011c) Inst: 800000b7
+Decode: curr_pc: 80000118
+Writing 00008000 to  3
+(80000110) WB Data: babebabe, to register: 29
+
+
+(8000011c) Inst: 800000b7
+Decode: curr_pc: 8000011c
+Writing 00008000 to 29
+(80000114) WB Data: babebabe, to register: 28
+
+
+(8000011c) Inst: 800000b7
+Decode: curr_pc: 8000011c
+Writing 00000005 to 28
+
+
+(80000120) Inst: 113
+Decode: curr_pc: 8000011c
+
+
+(80000124) Inst: 402081b3
+Decode: curr_pc: 80000120
+
+
+(80000128) Inst: 80000eb7
+Decode: curr_pc: 80000124
+(8000011c) WB Data: babebabe, to register:  1
+
+
+(8000012c) Inst: 600e13
+Decode: curr_pc: 80000128
+Writing 80000000 to  1
+(80000120) WB Data: babebabe, to register:  2
+
+
+(80000130) Inst: 45d19663
+Decode: curr_pc: 8000012c
+Writing 00000000 to  2
+(80000124) WB Data: babebabe, to register:  3
+
+
+(80000134) Inst: 800000b7
+Decode: curr_pc: 80000130
+Writing 80000000 to  3
+(80000128) WB Data: babebabe, to register: 29
+
+
+(80000134) Inst: 800000b7
+Decode: curr_pc: 80000134
+Writing 80000000 to 29
+(8000012c) WB Data: babebabe, to register: 28
+
+
+(80000134) Inst: 800000b7
+Decode: curr_pc: 80000134
+Writing 00000006 to 28
+
+
+(80000138) Inst: ffff8137
+Decode: curr_pc: 80000134
+
+
+(8000013c) Inst: 402081b3
+Decode: curr_pc: 80000138
+
+
+(80000140) Inst: 80008eb7
+Decode: curr_pc: 8000013c
+(80000134) WB Data: babebabe, to register:  1
+
+
+(80000144) Inst: 700e13
+Decode: curr_pc: 80000140
+Writing 80000000 to  1
+(80000138) WB Data: babebabe, to register:  2
+
+
+(80000148) Inst: 43d19a63
+Decode: curr_pc: 80000144
+Writing ffff8000 to  2
+(8000013c) WB Data: babebabe, to register:  3
+
+
+(8000014c) Inst: 93
+Decode: curr_pc: 80000148
+Writing 80008000 to  3
+(80000140) WB Data: babebabe, to register: 29
+
+
+(8000014c) Inst: 93
+Decode: curr_pc: 8000014c
+Writing 80008000 to 29
+(80000144) WB Data: babebabe, to register: 28
+
+
+(8000014c) Inst: 93
+Decode: curr_pc: 8000014c
+Writing 00000007 to 28
+
+
+(80000150) Inst: 8137
+Decode: curr_pc: 8000014c
+
+
+(80000154) Inst: fff10113
+Decode: curr_pc: 80000150
+
+
+(80000158) Inst: 402081b3
+Decode: curr_pc: 80000154
+(8000014c) WB Data: babebabe, to register:  1
+
+
+(8000015c) Inst: ffff8eb7
+Decode: curr_pc: 80000158
+Writing 00000000 to  1
+(80000150) WB Data: babebabe, to register:  2
+
+
+(80000160) Inst: 1e8e93
+Decode: curr_pc: 8000015c
+Writing 00008000 to  2
+(80000154) WB Data: babebabe, to register:  2
+
+
+(80000164) Inst: 800e13
+Decode: curr_pc: 80000160
+Writing 00007fff to  2
+(80000158) WB Data: babebabe, to register:  3
+
+
+(80000168) Inst: 41d19a63
+Decode: curr_pc: 80000164
+Writing ffff8001 to  3
+(8000015c) WB Data: babebabe, to register: 29
+
+
+(8000016c) Inst: 800000b7
+Decode: curr_pc: 80000168
+Writing ffff8000 to 29
+(80000160) WB Data: babebabe, to register: 29
+
+
+(8000016c) Inst: 800000b7
+Decode: curr_pc: 8000016c
+Writing ffff8001 to 29
+(80000164) WB Data: babebabe, to register: 28
+
+
+(8000016c) Inst: 800000b7
+Decode: curr_pc: 8000016c
+Writing 00000008 to 28
+
+
+(80000170) Inst: fff08093
+Decode: curr_pc: 8000016c
+
+
+(80000174) Inst: 113
+Decode: curr_pc: 80000170
+
+
+(80000178) Inst: 402081b3
+Decode: curr_pc: 80000174
+(8000016c) WB Data: babebabe, to register:  1
+
+
+(8000017c) Inst: 80000eb7
+Decode: curr_pc: 80000178
+Writing 80000000 to  1
+(80000170) WB Data: babebabe, to register:  1
+
+
+(80000180) Inst: fffe8e93
+Decode: curr_pc: 8000017c
+Writing 7fffffff to  1
+(80000174) WB Data: babebabe, to register:  2
+
+
+(80000184) Inst: 900e13
+Decode: curr_pc: 80000180
+Writing 00000000 to  2
+(80000178) WB Data: babebabe, to register:  3
+
+
+(80000188) Inst: 3fd19a63
+Decode: curr_pc: 80000184
+Writing 7fffffff to  3
+(8000017c) WB Data: babebabe, to register: 29
+
+
+(8000018c) Inst: 800000b7
+Decode: curr_pc: 80000188
+Writing 80000000 to 29
+(80000180) WB Data: babebabe, to register: 29
+
+
+(8000018c) Inst: 800000b7
+Decode: curr_pc: 8000018c
+Writing 7fffffff to 29
+(80000184) WB Data: babebabe, to register: 28
+
+
+(8000018c) Inst: 800000b7
+Decode: curr_pc: 8000018c
+Writing 00000009 to 28
+
+
+(80000190) Inst: fff08093
+Decode: curr_pc: 8000018c
+
+
+(80000194) Inst: 8137
+Decode: curr_pc: 80000190
+
+
+(80000198) Inst: fff10113
+Decode: curr_pc: 80000194
+(8000018c) WB Data: babebabe, to register:  1
+
+
+(8000019c) Inst: 402081b3
+Decode: curr_pc: 80000198
+Writing 80000000 to  1
+(80000190) WB Data: babebabe, to register:  1
+
+
+(800001a0) Inst: 7fff8eb7
+Decode: curr_pc: 8000019c
+Writing 7fffffff to  1
+(80000194) WB Data: babebabe, to register:  2
+
+
+(800001a4) Inst: a00e13
+Decode: curr_pc: 800001a0
+Writing 00008000 to  2
+(80000198) WB Data: babebabe, to register:  2
+
+
+(800001a8) Inst: 3dd19a63
+Decode: curr_pc: 800001a4
+Writing 00007fff to  2
+(8000019c) WB Data: babebabe, to register:  3
+
+
+(800001ac) Inst: 800000b7
+Decode: curr_pc: 800001a8
+Writing 7fff8000 to  3
+(800001a0) WB Data: babebabe, to register: 29
+
+
+(800001ac) Inst: 800000b7
+Decode: curr_pc: 800001ac
+Writing 7fff8000 to 29
+(800001a4) WB Data: babebabe, to register: 28
+
+
+(800001ac) Inst: 800000b7
+Decode: curr_pc: 800001ac
+Writing 0000000a to 28
+
+
+(800001b0) Inst: 8137
+Decode: curr_pc: 800001ac
+
+
+(800001b4) Inst: fff10113
+Decode: curr_pc: 800001b0
+
+
+(800001b8) Inst: 402081b3
+Decode: curr_pc: 800001b4
+(800001ac) WB Data: babebabe, to register:  1
+
+
+(800001bc) Inst: 7fff8eb7
+Decode: curr_pc: 800001b8
+Writing 80000000 to  1
+(800001b0) WB Data: babebabe, to register:  2
+
+
+(800001c0) Inst: 1e8e93
+Decode: curr_pc: 800001bc
+Writing 00008000 to  2
+(800001b4) WB Data: babebabe, to register:  2
+
+
+(800001c4) Inst: b00e13
+Decode: curr_pc: 800001c0
+Writing 00007fff to  2
+(800001b8) WB Data: babebabe, to register:  3
+
+
+(800001c8) Inst: 3bd19a63
+Decode: curr_pc: 800001c4
+Writing 7fff8001 to  3
+(800001bc) WB Data: babebabe, to register: 29
+
+
+(800001cc) Inst: 800000b7
+Decode: curr_pc: 800001c8
+Writing 7fff8000 to 29
+(800001c0) WB Data: babebabe, to register: 29
+
+
+(800001cc) Inst: 800000b7
+Decode: curr_pc: 800001cc
+Writing 7fff8001 to 29
+(800001c4) WB Data: babebabe, to register: 28
+
+
+(800001cc) Inst: 800000b7
+Decode: curr_pc: 800001cc
+Writing 0000000b to 28
+
+
+(800001d0) Inst: fff08093
+Decode: curr_pc: 800001cc
+
+
+(800001d4) Inst: ffff8137
+Decode: curr_pc: 800001d0
+
+
+(800001d8) Inst: 402081b3
+Decode: curr_pc: 800001d4
+(800001cc) WB Data: babebabe, to register:  1
+
+
+(800001dc) Inst: 80008eb7
+Decode: curr_pc: 800001d8
+Writing 80000000 to  1
+(800001d0) WB Data: babebabe, to register:  1
+
+
+(800001e0) Inst: fffe8e93
+Decode: curr_pc: 800001dc
+Writing 7fffffff to  1
+(800001d4) WB Data: babebabe, to register:  2
+
+
+(800001e4) Inst: c00e13
+Decode: curr_pc: 800001e0
+Writing ffff8000 to  2
+(800001d8) WB Data: babebabe, to register:  3
+
+
+(800001e8) Inst: 39d19a63
+Decode: curr_pc: 800001e4
+Writing 80007fff to  3
+(800001dc) WB Data: babebabe, to register: 29
+
+
+(800001ec) Inst: 93
+Decode: curr_pc: 800001e8
+Writing 80008000 to 29
+(800001e0) WB Data: babebabe, to register: 29
+
+
+(800001ec) Inst: 93
+Decode: curr_pc: 800001ec
+Writing 80007fff to 29
+(800001e4) WB Data: babebabe, to register: 28
+
+
+(800001ec) Inst: 93
+Decode: curr_pc: 800001ec
+Writing 0000000c to 28
+
+
+(800001f0) Inst: fff00113
+Decode: curr_pc: 800001ec
+
+
+(800001f4) Inst: 402081b3
+Decode: curr_pc: 800001f0
+
+
+(800001f8) Inst: 100e93
+Decode: curr_pc: 800001f4
+(800001ec) WB Data: babebabe, to register:  1
+
+
+(800001fc) Inst: d00e13
+Decode: curr_pc: 800001f8
+Writing 00000000 to  1
+(800001f0) WB Data: babebabe, to register:  2
+
+
+(80000200) Inst: 37d19e63
+Decode: curr_pc: 800001fc
+Writing ffffffff to  2
+(800001f4) WB Data: babebabe, to register:  3
+
+
+(80000204) Inst: fff00093
+Decode: curr_pc: 80000200
+Writing 00000001 to  3
+(800001f8) WB Data: babebabe, to register: 29
+
+
+(80000204) Inst: fff00093
+Decode: curr_pc: 80000204
+Writing 00000001 to 29
+(800001fc) WB Data: babebabe, to register: 28
+
+
+(80000204) Inst: fff00093
+Decode: curr_pc: 80000204
+Writing 0000000d to 28
+
+
+(80000208) Inst: 100113
+Decode: curr_pc: 80000204
+
+
+(8000020c) Inst: 402081b3
+Decode: curr_pc: 80000208
+
+
+(80000210) Inst: ffe00e93
+Decode: curr_pc: 8000020c
+(80000204) WB Data: babebabe, to register:  1
+
+
+(80000214) Inst: e00e13
+Decode: curr_pc: 80000210
+Writing ffffffff to  1
+(80000208) WB Data: babebabe, to register:  2
+
+
+(80000218) Inst: 37d19263
+Decode: curr_pc: 80000214
+Writing 00000001 to  2
+(8000020c) WB Data: babebabe, to register:  3
+
+
+(8000021c) Inst: fff00093
+Decode: curr_pc: 80000218
+Writing fffffffe to  3
+(80000210) WB Data: babebabe, to register: 29
+
+
+(8000021c) Inst: fff00093
+Decode: curr_pc: 8000021c
+Writing fffffffe to 29
+(80000214) WB Data: babebabe, to register: 28
+
+
+(8000021c) Inst: fff00093
+Decode: curr_pc: 8000021c
+Writing 0000000e to 28
+
+
+(80000220) Inst: fff00113
+Decode: curr_pc: 8000021c
+
+
+(80000224) Inst: 402081b3
+Decode: curr_pc: 80000220
+
+
+(80000228) Inst: e93
+Decode: curr_pc: 80000224
+(8000021c) WB Data: babebabe, to register:  1
+
+
+(8000022c) Inst: f00e13
+Decode: curr_pc: 80000228
+Writing ffffffff to  1
+(80000220) WB Data: babebabe, to register:  2
+
+
+(80000230) Inst: 35d19663
+Decode: curr_pc: 8000022c
+Writing ffffffff to  2
+(80000224) WB Data: babebabe, to register:  3
+
+
+(80000234) Inst: d00093
+Decode: curr_pc: 80000230
+Writing 00000000 to  3
+(80000228) WB Data: babebabe, to register: 29
+
+
+(80000234) Inst: d00093
+Decode: curr_pc: 80000234
+Writing 00000000 to 29
+(8000022c) WB Data: babebabe, to register: 28
+
+
+(80000234) Inst: d00093
+Decode: curr_pc: 80000234
+Writing 0000000f to 28
+
+
+(80000238) Inst: b00113
+Decode: curr_pc: 80000234
+
+
+(8000023c) Inst: 402080b3
+Decode: curr_pc: 80000238
+
+
+(80000240) Inst: 200e93
+Decode: curr_pc: 8000023c
+(80000234) WB Data: babebabe, to register:  1
+
+
+(80000244) Inst: 1000e13
+Decode: curr_pc: 80000240
+Writing 0000000d to  1
+(80000238) WB Data: babebabe, to register:  2
+
+
+(80000248) Inst: 33d09a63
+Decode: curr_pc: 80000244
+Writing 0000000b to  2
+(8000023c) WB Data: babebabe, to register:  1
+
+
+(8000024c) Inst: e00093
+Decode: curr_pc: 80000248
+Writing 00000002 to  1
+(80000240) WB Data: babebabe, to register: 29
+
+
+(8000024c) Inst: e00093
+Decode: curr_pc: 8000024c
+Writing 00000002 to 29
+(80000244) WB Data: babebabe, to register: 28
+
+
+(8000024c) Inst: e00093
+Decode: curr_pc: 8000024c
+Writing 00000010 to 28
+
+
+(80000250) Inst: b00113
+Decode: curr_pc: 8000024c
+
+
+(80000254) Inst: 40208133
+Decode: curr_pc: 80000250
+
+
+(80000258) Inst: 300e93
+Decode: curr_pc: 80000254
+(8000024c) WB Data: babebabe, to register:  1
+
+
+(8000025c) Inst: 1100e13
+Decode: curr_pc: 80000258
+Writing 0000000e to  1
+(80000250) WB Data: babebabe, to register:  2
+
+
+(80000260) Inst: 31d11e63
+Decode: curr_pc: 8000025c
+Writing 0000000b to  2
+(80000254) WB Data: babebabe, to register:  2
+
+
+(80000264) Inst: d00093
+Decode: curr_pc: 80000260
+Writing 00000003 to  2
+(80000258) WB Data: babebabe, to register: 29
+
+
+(80000264) Inst: d00093
+Decode: curr_pc: 80000264
+Writing 00000003 to 29
+(8000025c) WB Data: babebabe, to register: 28
+
+
+(80000264) Inst: d00093
+Decode: curr_pc: 80000264
+Writing 00000011 to 28
+
+
+(80000268) Inst: 401080b3
+Decode: curr_pc: 80000264
+
+
+(8000026c) Inst: e93
+Decode: curr_pc: 80000268
+
+
+(80000270) Inst: 1200e13
+Decode: curr_pc: 8000026c
+(80000264) WB Data: babebabe, to register:  1
+
+
+(80000274) Inst: 31d09463
+Decode: curr_pc: 80000270
+Writing 0000000d to  1
+(80000268) WB Data: babebabe, to register:  1
+
+
+(80000278) Inst: 213
+Decode: curr_pc: 80000274
+Writing 00000000 to  1
+(8000026c) WB Data: babebabe, to register: 29
+
+
+(80000278) Inst: 213
+Decode: curr_pc: 80000278
+Writing 00000000 to 29
+(80000270) WB Data: babebabe, to register: 28
+
+
+(80000278) Inst: 213
+Decode: curr_pc: 80000278
+Writing 00000012 to 28
+
+
+(8000027c) Inst: d00093
+Decode: curr_pc: 80000278
+
+
+(80000280) Inst: b00113
+Decode: curr_pc: 8000027c
+
+
+(80000284) Inst: 402081b3
+Decode: curr_pc: 80000280
+(80000278) WB Data: babebabe, to register:  4
+
+
+(80000288) Inst: 18313
+Decode: curr_pc: 80000284
+Writing 00000000 to  4
+(8000027c) WB Data: babebabe, to register:  1
+
+
+(8000028c) Inst: 120213
+Decode: curr_pc: 80000288
+Writing 0000000d to  1
+(80000280) WB Data: babebabe, to register:  2
+
+
+(80000290) Inst: 200293
+Decode: curr_pc: 8000028c
+Writing 0000000b to  2
+(80000284) WB Data: babebabe, to register:  3
+
+
+(80000294) Inst: fe5214e3
+Decode: curr_pc: 80000290
+Writing 00000002 to  3
+(80000288) WB Data: babebabe, to register:  6
+
+
+(80000298) Inst: 200e93
+Decode: curr_pc: 80000294
+Writing 00000002 to  6
+(8000028c) WB Data: babebabe, to register:  4
+
+
+(80000298) Inst: 200e93
+Decode: curr_pc: 80000298
+Writing 00000001 to  4
+(80000290) WB Data: babebabe, to register:  5
+
+
+(8000027c) Inst: d00093
+Decode: curr_pc: 80000298
+Writing 00000002 to  5
+
+
+(80000280) Inst: b00113
+Decode: curr_pc: 8000027c
+
+
+(80000284) Inst: 402081b3
+Decode: curr_pc: 80000280
+
+
+(80000288) Inst: 18313
+Decode: curr_pc: 80000284
+(8000027c) WB Data: babebabe, to register:  1
+
+
+(8000028c) Inst: 120213
+Decode: curr_pc: 80000288
+Writing 0000000d to  1
+(80000280) WB Data: babebabe, to register:  2
+
+
+(80000290) Inst: 200293
+Decode: curr_pc: 8000028c
+Writing 0000000b to  2
+(80000284) WB Data: babebabe, to register:  3
+
+
+(80000294) Inst: fe5214e3
+Decode: curr_pc: 80000290
+Writing 00000002 to  3
+(80000288) WB Data: babebabe, to register:  6
+
+
+(80000298) Inst: 200e93
+Decode: curr_pc: 80000294
+Writing 00000002 to  6
+(8000028c) WB Data: babebabe, to register:  4
+
+
+(80000298) Inst: 200e93
+Decode: curr_pc: 80000298
+Writing 00000002 to  4
+(80000290) WB Data: babebabe, to register:  5
+
+
+(80000298) Inst: 200e93
+Decode: curr_pc: 80000298
+Writing 00000002 to  5
+
+
+(8000029c) Inst: 1300e13
+Decode: curr_pc: 80000298
+
+
+(800002a0) Inst: 2dd31e63
+Decode: curr_pc: 8000029c
+
+
+(800002a4) Inst: 213
+Decode: curr_pc: 800002a0
+(80000298) WB Data: babebabe, to register: 29
+
+
+(800002a4) Inst: 213
+Decode: curr_pc: 800002a4
+Writing 00000002 to 29
+(8000029c) WB Data: babebabe, to register: 28
+
+
+(800002a4) Inst: 213
+Decode: curr_pc: 800002a4
+Writing 00000013 to 28
+
+
+(800002a8) Inst: e00093
+Decode: curr_pc: 800002a4
+
+
+(800002ac) Inst: b00113
+Decode: curr_pc: 800002a8
+
+
+(800002b0) Inst: 402081b3
+Decode: curr_pc: 800002ac
+(800002a4) WB Data: babebabe, to register:  4
+
+
+(800002b4) Inst: 13
+Decode: curr_pc: 800002b0
+Writing 00000000 to  4
+(800002a8) WB Data: babebabe, to register:  1
+
+
+(800002b8) Inst: 18313
+Decode: curr_pc: 800002b4
+Writing 0000000e to  1
+(800002ac) WB Data: babebabe, to register:  2
+
+
+(800002bc) Inst: 120213
+Decode: curr_pc: 800002b8
+Writing 0000000b to  2
+(800002b0) WB Data: babebabe, to register:  3
+
+
+(800002c0) Inst: 200293
+Decode: curr_pc: 800002bc
+Writing 00000003 to  3
+(800002b4) WB Data: babebabe, to register:  0
+
+
+(800002c4) Inst: fe5212e3
+Decode: curr_pc: 800002c0
+(800002b8) WB Data: babebabe, to register:  6
+
+
+(800002c8) Inst: 300e93
+Decode: curr_pc: 800002c4
+Writing 00000003 to  6
+(800002bc) WB Data: babebabe, to register:  4
+
+
+(800002c8) Inst: 300e93
+Decode: curr_pc: 800002c8
+Writing 00000001 to  4
+(800002c0) WB Data: babebabe, to register:  5
+
+
+(800002a8) Inst: e00093
+Decode: curr_pc: 800002c8
+Writing 00000002 to  5
+
+
+(800002ac) Inst: b00113
+Decode: curr_pc: 800002a8
+
+
+(800002b0) Inst: 402081b3
+Decode: curr_pc: 800002ac
+
+
+(800002b4) Inst: 13
+Decode: curr_pc: 800002b0
+(800002a8) WB Data: babebabe, to register:  1
+
+
+(800002b8) Inst: 18313
+Decode: curr_pc: 800002b4
+Writing 0000000e to  1
+(800002ac) WB Data: babebabe, to register:  2
+
+
+(800002bc) Inst: 120213
+Decode: curr_pc: 800002b8
+Writing 0000000b to  2
+(800002b0) WB Data: babebabe, to register:  3
+
+
+(800002c0) Inst: 200293
+Decode: curr_pc: 800002bc
+Writing 00000003 to  3
+(800002b4) WB Data: babebabe, to register:  0
+
+
+(800002c4) Inst: fe5212e3
+Decode: curr_pc: 800002c0
+(800002b8) WB Data: babebabe, to register:  6
+
+
+(800002c8) Inst: 300e93
+Decode: curr_pc: 800002c4
+Writing 00000003 to  6
+(800002bc) WB Data: babebabe, to register:  4
+
+
+(800002c8) Inst: 300e93
+Decode: curr_pc: 800002c8
+Writing 00000002 to  4
+(800002c0) WB Data: babebabe, to register:  5
+
+
+(800002c8) Inst: 300e93
+Decode: curr_pc: 800002c8
+Writing 00000002 to  5
+
+
+(800002cc) Inst: 1400e13
+Decode: curr_pc: 800002c8
+
+
+(800002d0) Inst: 2bd31663
+Decode: curr_pc: 800002cc
+
+
+(800002d4) Inst: 213
+Decode: curr_pc: 800002d0
+(800002c8) WB Data: babebabe, to register: 29
+
+
+(800002d4) Inst: 213
+Decode: curr_pc: 800002d4
+Writing 00000003 to 29
+(800002cc) WB Data: babebabe, to register: 28
+
+
+(800002d4) Inst: 213
+Decode: curr_pc: 800002d4
+Writing 00000014 to 28
+
+
+(800002d8) Inst: f00093
+Decode: curr_pc: 800002d4
+
+
+(800002dc) Inst: b00113
+Decode: curr_pc: 800002d8
+
+
+(800002e0) Inst: 402081b3
+Decode: curr_pc: 800002dc
+(800002d4) WB Data: babebabe, to register:  4
+
+
+(800002e4) Inst: 13
+Decode: curr_pc: 800002e0
+Writing 00000000 to  4
+(800002d8) WB Data: babebabe, to register:  1
+
+
+(800002e8) Inst: 13
+Decode: curr_pc: 800002e4
+Writing 0000000f to  1
+(800002dc) WB Data: babebabe, to register:  2
+
+
+(800002ec) Inst: 18313
+Decode: curr_pc: 800002e8
+Writing 0000000b to  2
+(800002e0) WB Data: babebabe, to register:  3
+
+
+(800002f0) Inst: 120213
+Decode: curr_pc: 800002ec
+Writing 00000004 to  3
+(800002e4) WB Data: babebabe, to register:  0
+
+
+(800002f4) Inst: 200293
+Decode: curr_pc: 800002f0
+(800002e8) WB Data: babebabe, to register:  0
+
+
+(800002f8) Inst: fe5210e3
+Decode: curr_pc: 800002f4
+(800002ec) WB Data: babebabe, to register:  6
+
+
+(800002fc) Inst: 400e93
+Decode: curr_pc: 800002f8
+Writing 00000004 to  6
+(800002f0) WB Data: babebabe, to register:  4
+
+
+(800002fc) Inst: 400e93
+Decode: curr_pc: 800002fc
+Writing 00000001 to  4
+(800002f4) WB Data: babebabe, to register:  5
+
+
+(800002d8) Inst: f00093
+Decode: curr_pc: 800002fc
+Writing 00000002 to  5
+
+
+(800002dc) Inst: b00113
+Decode: curr_pc: 800002d8
+
+
+(800002e0) Inst: 402081b3
+Decode: curr_pc: 800002dc
+
+
+(800002e4) Inst: 13
+Decode: curr_pc: 800002e0
+(800002d8) WB Data: babebabe, to register:  1
+
+
+(800002e8) Inst: 13
+Decode: curr_pc: 800002e4
+Writing 0000000f to  1
+(800002dc) WB Data: babebabe, to register:  2
+
+
+(800002ec) Inst: 18313
+Decode: curr_pc: 800002e8
+Writing 0000000b to  2
+(800002e0) WB Data: babebabe, to register:  3
+
+
+(800002f0) Inst: 120213
+Decode: curr_pc: 800002ec
+Writing 00000004 to  3
+(800002e4) WB Data: babebabe, to register:  0
+
+
+(800002f4) Inst: 200293
+Decode: curr_pc: 800002f0
+(800002e8) WB Data: babebabe, to register:  0
+
+
+(800002f8) Inst: fe5210e3
+Decode: curr_pc: 800002f4
+(800002ec) WB Data: babebabe, to register:  6
+
+
+(800002fc) Inst: 400e93
+Decode: curr_pc: 800002f8
+Writing 00000004 to  6
+(800002f0) WB Data: babebabe, to register:  4
+
+
+(800002fc) Inst: 400e93
+Decode: curr_pc: 800002fc
+Writing 00000002 to  4
+(800002f4) WB Data: babebabe, to register:  5
+
+
+(800002fc) Inst: 400e93
+Decode: curr_pc: 800002fc
+Writing 00000002 to  5
+
+
+(80000300) Inst: 1500e13
+Decode: curr_pc: 800002fc
+
+
+(80000304) Inst: 27d31c63
+Decode: curr_pc: 80000300
+
+
+(80000308) Inst: 213
+Decode: curr_pc: 80000304
+(800002fc) WB Data: babebabe, to register: 29
+
+
+(80000308) Inst: 213
+Decode: curr_pc: 80000308
+Writing 00000004 to 29
+(80000300) WB Data: babebabe, to register: 28
+
+
+(80000308) Inst: 213
+Decode: curr_pc: 80000308
+Writing 00000015 to 28
+
+
+(8000030c) Inst: d00093
+Decode: curr_pc: 80000308
+
+
+(80000310) Inst: b00113
+Decode: curr_pc: 8000030c
+
+
+(80000314) Inst: 402081b3
+Decode: curr_pc: 80000310
+(80000308) WB Data: babebabe, to register:  4
+
+
+(80000318) Inst: 120213
+Decode: curr_pc: 80000314
+Writing 00000000 to  4
+(8000030c) WB Data: babebabe, to register:  1
+
+
+(8000031c) Inst: 200293
+Decode: curr_pc: 80000318
+Writing 0000000d to  1
+(80000310) WB Data: babebabe, to register:  2
+
+
+(80000320) Inst: fe5216e3
+Decode: curr_pc: 8000031c
+Writing 0000000b to  2
+(80000314) WB Data: babebabe, to register:  3
+
+
+(80000324) Inst: 200e93
+Decode: curr_pc: 80000320
+Writing 00000002 to  3
+(80000318) WB Data: babebabe, to register:  4
+
+
+(80000324) Inst: 200e93
+Decode: curr_pc: 80000324
+Writing 00000001 to  4
+(8000031c) WB Data: babebabe, to register:  5
+
+
+(8000030c) Inst: d00093
+Decode: curr_pc: 80000324
+Writing 00000002 to  5
+
+
+(80000310) Inst: b00113
+Decode: curr_pc: 8000030c
+
+
+(80000314) Inst: 402081b3
+Decode: curr_pc: 80000310
+
+
+(80000318) Inst: 120213
+Decode: curr_pc: 80000314
+(8000030c) WB Data: babebabe, to register:  1
+
+
+(8000031c) Inst: 200293
+Decode: curr_pc: 80000318
+Writing 0000000d to  1
+(80000310) WB Data: babebabe, to register:  2
+
+
+(80000320) Inst: fe5216e3
+Decode: curr_pc: 8000031c
+Writing 0000000b to  2
+(80000314) WB Data: babebabe, to register:  3
+
+
+(80000324) Inst: 200e93
+Decode: curr_pc: 80000320
+Writing 00000002 to  3
+(80000318) WB Data: babebabe, to register:  4
+
+
+(80000324) Inst: 200e93
+Decode: curr_pc: 80000324
+Writing 00000002 to  4
+(8000031c) WB Data: babebabe, to register:  5
+
+
+(80000324) Inst: 200e93
+Decode: curr_pc: 80000324
+Writing 00000002 to  5
+
+
+(80000328) Inst: 1600e13
+Decode: curr_pc: 80000324
+
+
+(8000032c) Inst: 25d19863
+Decode: curr_pc: 80000328
+
+
+(80000330) Inst: 213
+Decode: curr_pc: 8000032c
+(80000324) WB Data: babebabe, to register: 29
+
+
+(80000330) Inst: 213
+Decode: curr_pc: 80000330
+Writing 00000002 to 29
+(80000328) WB Data: babebabe, to register: 28
+
+
+(80000330) Inst: 213
+Decode: curr_pc: 80000330
+Writing 00000016 to 28
+
+
+(80000334) Inst: e00093
+Decode: curr_pc: 80000330
+
+
+(80000338) Inst: b00113
+Decode: curr_pc: 80000334
+
+
+(8000033c) Inst: 13
+Decode: curr_pc: 80000338
+(80000330) WB Data: babebabe, to register:  4
+
+
+(80000340) Inst: 402081b3
+Decode: curr_pc: 8000033c
+Writing 00000000 to  4
+(80000334) WB Data: babebabe, to register:  1
+
+
+(80000344) Inst: 120213
+Decode: curr_pc: 80000340
+Writing 0000000e to  1
+(80000338) WB Data: babebabe, to register:  2
+
+
+(80000348) Inst: 200293
+Decode: curr_pc: 80000344
+Writing 0000000b to  2
+(8000033c) WB Data: babebabe, to register:  0
+
+
+(8000034c) Inst: fe5214e3
+Decode: curr_pc: 80000348
+(80000340) WB Data: babebabe, to register:  3
+
+
+(80000350) Inst: 300e93
+Decode: curr_pc: 8000034c
+Writing 00000003 to  3
+(80000344) WB Data: babebabe, to register:  4
+
+
+(80000350) Inst: 300e93
+Decode: curr_pc: 80000350
+Writing 00000001 to  4
+(80000348) WB Data: babebabe, to register:  5
+
+
+(80000334) Inst: e00093
+Decode: curr_pc: 80000350
+Writing 00000002 to  5
+
+
+(80000338) Inst: b00113
+Decode: curr_pc: 80000334
+
+
+(8000033c) Inst: 13
+Decode: curr_pc: 80000338
+
+
+(80000340) Inst: 402081b3
+Decode: curr_pc: 8000033c
+(80000334) WB Data: babebabe, to register:  1
+
+
+(80000344) Inst: 120213
+Decode: curr_pc: 80000340
+Writing 0000000e to  1
+(80000338) WB Data: babebabe, to register:  2
+
+
+(80000348) Inst: 200293
+Decode: curr_pc: 80000344
+Writing 0000000b to  2
+(8000033c) WB Data: babebabe, to register:  0
+
+
+(8000034c) Inst: fe5214e3
+Decode: curr_pc: 80000348
+(80000340) WB Data: babebabe, to register:  3
+
+
+(80000350) Inst: 300e93
+Decode: curr_pc: 8000034c
+Writing 00000003 to  3
+(80000344) WB Data: babebabe, to register:  4
+
+
+(80000350) Inst: 300e93
+Decode: curr_pc: 80000350
+Writing 00000002 to  4
+(80000348) WB Data: babebabe, to register:  5
+
+
+(80000350) Inst: 300e93
+Decode: curr_pc: 80000350
+Writing 00000002 to  5
+
+
+(80000354) Inst: 1700e13
+Decode: curr_pc: 80000350
+
+
+(80000358) Inst: 23d19263
+Decode: curr_pc: 80000354
+
+
+(8000035c) Inst: 213
+Decode: curr_pc: 80000358
+(80000350) WB Data: babebabe, to register: 29
+
+
+(8000035c) Inst: 213
+Decode: curr_pc: 8000035c
+Writing 00000003 to 29
+(80000354) WB Data: babebabe, to register: 28
+
+
+(8000035c) Inst: 213
+Decode: curr_pc: 8000035c
+Writing 00000017 to 28
+
+
+(80000360) Inst: f00093
+Decode: curr_pc: 8000035c
+
+
+(80000364) Inst: b00113
+Decode: curr_pc: 80000360
+
+
+(80000368) Inst: 13
+Decode: curr_pc: 80000364
+(8000035c) WB Data: babebabe, to register:  4
+
+
+(8000036c) Inst: 13
+Decode: curr_pc: 80000368
+Writing 00000000 to  4
+(80000360) WB Data: babebabe, to register:  1
+
+
+(80000370) Inst: 402081b3
+Decode: curr_pc: 8000036c
+Writing 0000000f to  1
+(80000364) WB Data: babebabe, to register:  2
+
+
+(80000374) Inst: 120213
+Decode: curr_pc: 80000370
+Writing 0000000b to  2
+(80000368) WB Data: babebabe, to register:  0
+
+
+(80000378) Inst: 200293
+Decode: curr_pc: 80000374
+(8000036c) WB Data: babebabe, to register:  0
+
+
+(8000037c) Inst: fe5212e3
+Decode: curr_pc: 80000378
+(80000370) WB Data: babebabe, to register:  3
+
+
+(80000380) Inst: 400e93
+Decode: curr_pc: 8000037c
+Writing 00000004 to  3
+(80000374) WB Data: babebabe, to register:  4
+
+
+(80000380) Inst: 400e93
+Decode: curr_pc: 80000380
+Writing 00000001 to  4
+(80000378) WB Data: babebabe, to register:  5
+
+
+(80000360) Inst: f00093
+Decode: curr_pc: 80000380
+Writing 00000002 to  5
+
+
+(80000364) Inst: b00113
+Decode: curr_pc: 80000360
+
+
+(80000368) Inst: 13
+Decode: curr_pc: 80000364
+
+
+(8000036c) Inst: 13
+Decode: curr_pc: 80000368
+(80000360) WB Data: babebabe, to register:  1
+
+
+(80000370) Inst: 402081b3
+Decode: curr_pc: 8000036c
+Writing 0000000f to  1
+(80000364) WB Data: babebabe, to register:  2
+
+
+(80000374) Inst: 120213
+Decode: curr_pc: 80000370
+Writing 0000000b to  2
+(80000368) WB Data: babebabe, to register:  0
+
+
+(80000378) Inst: 200293
+Decode: curr_pc: 80000374
+(8000036c) WB Data: babebabe, to register:  0
+
+
+(8000037c) Inst: fe5212e3
+Decode: curr_pc: 80000378
+(80000370) WB Data: babebabe, to register:  3
+
+
+(80000380) Inst: 400e93
+Decode: curr_pc: 8000037c
+Writing 00000004 to  3
+(80000374) WB Data: babebabe, to register:  4
+
+
+(80000380) Inst: 400e93
+Decode: curr_pc: 80000380
+Writing 00000002 to  4
+(80000378) WB Data: babebabe, to register:  5
+
+
+(80000380) Inst: 400e93
+Decode: curr_pc: 80000380
+Writing 00000002 to  5
+
+
+(80000384) Inst: 1800e13
+Decode: curr_pc: 80000380
+
+
+(80000388) Inst: 1fd19a63
+Decode: curr_pc: 80000384
+
+
+(8000038c) Inst: 213
+Decode: curr_pc: 80000388
+(80000380) WB Data: babebabe, to register: 29
+
+
+(8000038c) Inst: 213
+Decode: curr_pc: 8000038c
+Writing 00000004 to 29
+(80000384) WB Data: babebabe, to register: 28
+
+
+(8000038c) Inst: 213
+Decode: curr_pc: 8000038c
+Writing 00000018 to 28
+
+
+(80000390) Inst: d00093
+Decode: curr_pc: 8000038c
+
+
+(80000394) Inst: 13
+Decode: curr_pc: 80000390
+
+
+(80000398) Inst: b00113
+Decode: curr_pc: 80000394
+(8000038c) WB Data: babebabe, to register:  4
+
+
+(8000039c) Inst: 402081b3
+Decode: curr_pc: 80000398
+Writing 00000000 to  4
+(80000390) WB Data: babebabe, to register:  1
+
+
+(800003a0) Inst: 120213
+Decode: curr_pc: 8000039c
+Writing 0000000d to  1
+(80000394) WB Data: babebabe, to register:  0
+
+
+(800003a4) Inst: 200293
+Decode: curr_pc: 800003a0
+(80000398) WB Data: babebabe, to register:  2
+
+
+(800003a8) Inst: fe5214e3
+Decode: curr_pc: 800003a4
+Writing 0000000b to  2
+(8000039c) WB Data: babebabe, to register:  3
+
+
+(800003ac) Inst: 200e93
+Decode: curr_pc: 800003a8
+Writing 00000002 to  3
+(800003a0) WB Data: babebabe, to register:  4
+
+
+(800003ac) Inst: 200e93
+Decode: curr_pc: 800003ac
+Writing 00000001 to  4
+(800003a4) WB Data: babebabe, to register:  5
+
+
+(80000390) Inst: d00093
+Decode: curr_pc: 800003ac
+Writing 00000002 to  5
+
+
+(80000394) Inst: 13
+Decode: curr_pc: 80000390
+
+
+(80000398) Inst: b00113
+Decode: curr_pc: 80000394
+
+
+(8000039c) Inst: 402081b3
+Decode: curr_pc: 80000398
+(80000390) WB Data: babebabe, to register:  1
+
+
+(800003a0) Inst: 120213
+Decode: curr_pc: 8000039c
+Writing 0000000d to  1
+(80000394) WB Data: babebabe, to register:  0
+
+
+(800003a4) Inst: 200293
+Decode: curr_pc: 800003a0
+(80000398) WB Data: babebabe, to register:  2
+
+
+(800003a8) Inst: fe5214e3
+Decode: curr_pc: 800003a4
+Writing 0000000b to  2
+(8000039c) WB Data: babebabe, to register:  3
+
+
+(800003ac) Inst: 200e93
+Decode: curr_pc: 800003a8
+Writing 00000002 to  3
+(800003a0) WB Data: babebabe, to register:  4
+
+
+(800003ac) Inst: 200e93
+Decode: curr_pc: 800003ac
+Writing 00000002 to  4
+(800003a4) WB Data: babebabe, to register:  5
+
+
+(800003ac) Inst: 200e93
+Decode: curr_pc: 800003ac
+Writing 00000002 to  5
+
+
+(800003b0) Inst: 1900e13
+Decode: curr_pc: 800003ac
+
+
+(800003b4) Inst: 1dd19463
+Decode: curr_pc: 800003b0
+
+
+(800003b8) Inst: 213
+Decode: curr_pc: 800003b4
+(800003ac) WB Data: babebabe, to register: 29
+
+
+(800003b8) Inst: 213
+Decode: curr_pc: 800003b8
+Writing 00000002 to 29
+(800003b0) WB Data: babebabe, to register: 28
+
+
+(800003b8) Inst: 213
+Decode: curr_pc: 800003b8
+Writing 00000019 to 28
+
+
+(800003bc) Inst: e00093
+Decode: curr_pc: 800003b8
+
+
+(800003c0) Inst: 13
+Decode: curr_pc: 800003bc
+
+
+(800003c4) Inst: b00113
+Decode: curr_pc: 800003c0
+(800003b8) WB Data: babebabe, to register:  4
+
+
+(800003c8) Inst: 13
+Decode: curr_pc: 800003c4
+Writing 00000000 to  4
+(800003bc) WB Data: babebabe, to register:  1
+
+
+(800003cc) Inst: 402081b3
+Decode: curr_pc: 800003c8
+Writing 0000000e to  1
+(800003c0) WB Data: babebabe, to register:  0
+
+
+(800003d0) Inst: 120213
+Decode: curr_pc: 800003cc
+(800003c4) WB Data: babebabe, to register:  2
+
+
+(800003d4) Inst: 200293
+Decode: curr_pc: 800003d0
+Writing 0000000b to  2
+(800003c8) WB Data: babebabe, to register:  0
+
+
+(800003d8) Inst: fe5212e3
+Decode: curr_pc: 800003d4
+(800003cc) WB Data: babebabe, to register:  3
+
+
+(800003dc) Inst: 300e93
+Decode: curr_pc: 800003d8
+Writing 00000003 to  3
+(800003d0) WB Data: babebabe, to register:  4
+
+
+(800003dc) Inst: 300e93
+Decode: curr_pc: 800003dc
+Writing 00000001 to  4
+(800003d4) WB Data: babebabe, to register:  5
+
+
+(800003bc) Inst: e00093
+Decode: curr_pc: 800003dc
+Writing 00000002 to  5
+
+
+(800003c0) Inst: 13
+Decode: curr_pc: 800003bc
+
+
+(800003c4) Inst: b00113
+Decode: curr_pc: 800003c0
+
+
+(800003c8) Inst: 13
+Decode: curr_pc: 800003c4
+(800003bc) WB Data: babebabe, to register:  1
+
+
+(800003cc) Inst: 402081b3
+Decode: curr_pc: 800003c8
+Writing 0000000e to  1
+(800003c0) WB Data: babebabe, to register:  0
+
+
+(800003d0) Inst: 120213
+Decode: curr_pc: 800003cc
+(800003c4) WB Data: babebabe, to register:  2
+
+
+(800003d4) Inst: 200293
+Decode: curr_pc: 800003d0
+Writing 0000000b to  2
+(800003c8) WB Data: babebabe, to register:  0
+
+
+(800003d8) Inst: fe5212e3
+Decode: curr_pc: 800003d4
+(800003cc) WB Data: babebabe, to register:  3
+
+
+(800003dc) Inst: 300e93
+Decode: curr_pc: 800003d8
+Writing 00000003 to  3
+(800003d0) WB Data: babebabe, to register:  4
+
+
+(800003dc) Inst: 300e93
+Decode: curr_pc: 800003dc
+Writing 00000002 to  4
+(800003d4) WB Data: babebabe, to register:  5
+
+
+(800003dc) Inst: 300e93
+Decode: curr_pc: 800003dc
+Writing 00000002 to  5
+
+
+(800003e0) Inst: 1a00e13
+Decode: curr_pc: 800003dc
+
+
+(800003e4) Inst: 19d19c63
+Decode: curr_pc: 800003e0
+
+
+(800003e8) Inst: 213
+Decode: curr_pc: 800003e4
+(800003dc) WB Data: babebabe, to register: 29
+
+
+(800003e8) Inst: 213
+Decode: curr_pc: 800003e8
+Writing 00000003 to 29
+(800003e0) WB Data: babebabe, to register: 28
+
+
+(800003e8) Inst: 213
+Decode: curr_pc: 800003e8
+Writing 0000001a to 28
+
+
+(800003ec) Inst: f00093
+Decode: curr_pc: 800003e8
+
+
+(800003f0) Inst: 13
+Decode: curr_pc: 800003ec
+
+
+(800003f4) Inst: 13
+Decode: curr_pc: 800003f0
+(800003e8) WB Data: babebabe, to register:  4
+
+
+(800003f8) Inst: b00113
+Decode: curr_pc: 800003f4
+Writing 00000000 to  4
+(800003ec) WB Data: babebabe, to register:  1
+
+
+(800003fc) Inst: 402081b3
+Decode: curr_pc: 800003f8
+Writing 0000000f to  1
+(800003f0) WB Data: babebabe, to register:  0
+
+
+(80000400) Inst: 120213
+Decode: curr_pc: 800003fc
+(800003f4) WB Data: babebabe, to register:  0
+
+
+(80000404) Inst: 200293
+Decode: curr_pc: 80000400
+(800003f8) WB Data: babebabe, to register:  2
+
+
+(80000408) Inst: fe5212e3
+Decode: curr_pc: 80000404
+Writing 0000000b to  2
+(800003fc) WB Data: babebabe, to register:  3
+
+
+(8000040c) Inst: 400e93
+Decode: curr_pc: 80000408
+Writing 00000004 to  3
+(80000400) WB Data: babebabe, to register:  4
+
+
+(8000040c) Inst: 400e93
+Decode: curr_pc: 8000040c
+Writing 00000001 to  4
+(80000404) WB Data: babebabe, to register:  5
+
+
+(800003ec) Inst: f00093
+Decode: curr_pc: 8000040c
+Writing 00000002 to  5
+
+
+(800003f0) Inst: 13
+Decode: curr_pc: 800003ec
+
+
+(800003f4) Inst: 13
+Decode: curr_pc: 800003f0
+
+
+(800003f8) Inst: b00113
+Decode: curr_pc: 800003f4
+(800003ec) WB Data: babebabe, to register:  1
+
+
+(800003fc) Inst: 402081b3
+Decode: curr_pc: 800003f8
+Writing 0000000f to  1
+(800003f0) WB Data: babebabe, to register:  0
+
+
+(80000400) Inst: 120213
+Decode: curr_pc: 800003fc
+(800003f4) WB Data: babebabe, to register:  0
+
+
+(80000404) Inst: 200293
+Decode: curr_pc: 80000400
+(800003f8) WB Data: babebabe, to register:  2
+
+
+(80000408) Inst: fe5212e3
+Decode: curr_pc: 80000404
+Writing 0000000b to  2
+(800003fc) WB Data: babebabe, to register:  3
+
+
+(8000040c) Inst: 400e93
+Decode: curr_pc: 80000408
+Writing 00000004 to  3
+(80000400) WB Data: babebabe, to register:  4
+
+
+(8000040c) Inst: 400e93
+Decode: curr_pc: 8000040c
+Writing 00000002 to  4
+(80000404) WB Data: babebabe, to register:  5
+
+
+(8000040c) Inst: 400e93
+Decode: curr_pc: 8000040c
+Writing 00000002 to  5
+
+
+(80000410) Inst: 1b00e13
+Decode: curr_pc: 8000040c
+
+
+(80000414) Inst: 17d19463
+Decode: curr_pc: 80000410
+
+
+(80000418) Inst: 213
+Decode: curr_pc: 80000414
+(8000040c) WB Data: babebabe, to register: 29
+
+
+(80000418) Inst: 213
+Decode: curr_pc: 80000418
+Writing 00000004 to 29
+(80000410) WB Data: babebabe, to register: 28
+
+
+(80000418) Inst: 213
+Decode: curr_pc: 80000418
+Writing 0000001b to 28
+
+
+(8000041c) Inst: b00113
+Decode: curr_pc: 80000418
+
+
+(80000420) Inst: d00093
+Decode: curr_pc: 8000041c
+
+
+(80000424) Inst: 402081b3
+Decode: curr_pc: 80000420
+(80000418) WB Data: babebabe, to register:  4
+
+
+(80000428) Inst: 120213
+Decode: curr_pc: 80000424
+Writing 00000000 to  4
+(8000041c) WB Data: babebabe, to register:  2
+
+
+(8000042c) Inst: 200293
+Decode: curr_pc: 80000428
+Writing 0000000b to  2
+(80000420) WB Data: babebabe, to register:  1
+
+
+(80000430) Inst: fe5216e3
+Decode: curr_pc: 8000042c
+Writing 0000000d to  1
+(80000424) WB Data: babebabe, to register:  3
+
+
+(80000434) Inst: 200e93
+Decode: curr_pc: 80000430
+Writing 00000002 to  3
+(80000428) WB Data: babebabe, to register:  4
+
+
+(80000434) Inst: 200e93
+Decode: curr_pc: 80000434
+Writing 00000001 to  4
+(8000042c) WB Data: babebabe, to register:  5
+
+
+(8000041c) Inst: b00113
+Decode: curr_pc: 80000434
+Writing 00000002 to  5
+
+
+(80000420) Inst: d00093
+Decode: curr_pc: 8000041c
+
+
+(80000424) Inst: 402081b3
+Decode: curr_pc: 80000420
+
+
+(80000428) Inst: 120213
+Decode: curr_pc: 80000424
+(8000041c) WB Data: babebabe, to register:  2
+
+
+(8000042c) Inst: 200293
+Decode: curr_pc: 80000428
+Writing 0000000b to  2
+(80000420) WB Data: babebabe, to register:  1
+
+
+(80000430) Inst: fe5216e3
+Decode: curr_pc: 8000042c
+Writing 0000000d to  1
+(80000424) WB Data: babebabe, to register:  3
+
+
+(80000434) Inst: 200e93
+Decode: curr_pc: 80000430
+Writing 00000002 to  3
+(80000428) WB Data: babebabe, to register:  4
+
+
+(80000434) Inst: 200e93
+Decode: curr_pc: 80000434
+Writing 00000002 to  4
+(8000042c) WB Data: babebabe, to register:  5
+
+
+(80000434) Inst: 200e93
+Decode: curr_pc: 80000434
+Writing 00000002 to  5
+
+
+(80000438) Inst: 1c00e13
+Decode: curr_pc: 80000434
+
+
+(8000043c) Inst: 15d19063
+Decode: curr_pc: 80000438
+
+
+(80000440) Inst: 213
+Decode: curr_pc: 8000043c
+(80000434) WB Data: babebabe, to register: 29
+
+
+(80000440) Inst: 213
+Decode: curr_pc: 80000440
+Writing 00000002 to 29
+(80000438) WB Data: babebabe, to register: 28
+
+
+(80000440) Inst: 213
+Decode: curr_pc: 80000440
+Writing 0000001c to 28
+
+
+(80000444) Inst: b00113
+Decode: curr_pc: 80000440
+
+
+(80000448) Inst: e00093
+Decode: curr_pc: 80000444
+
+
+(8000044c) Inst: 13
+Decode: curr_pc: 80000448
+(80000440) WB Data: babebabe, to register:  4
+
+
+(80000450) Inst: 402081b3
+Decode: curr_pc: 8000044c
+Writing 00000000 to  4
+(80000444) WB Data: babebabe, to register:  2
+
+
+(80000454) Inst: 120213
+Decode: curr_pc: 80000450
+Writing 0000000b to  2
+(80000448) WB Data: babebabe, to register:  1
+
+
+(80000458) Inst: 200293
+Decode: curr_pc: 80000454
+Writing 0000000e to  1
+(8000044c) WB Data: babebabe, to register:  0
+
+
+(8000045c) Inst: fe5214e3
+Decode: curr_pc: 80000458
+(80000450) WB Data: babebabe, to register:  3
+
+
+(80000460) Inst: 300e93
+Decode: curr_pc: 8000045c
+Writing 00000003 to  3
+(80000454) WB Data: babebabe, to register:  4
+
+
+(80000460) Inst: 300e93
+Decode: curr_pc: 80000460
+Writing 00000001 to  4
+(80000458) WB Data: babebabe, to register:  5
+
+
+(80000444) Inst: b00113
+Decode: curr_pc: 80000460
+Writing 00000002 to  5
+
+
+(80000448) Inst: e00093
+Decode: curr_pc: 80000444
+
+
+(8000044c) Inst: 13
+Decode: curr_pc: 80000448
+
+
+(80000450) Inst: 402081b3
+Decode: curr_pc: 8000044c
+(80000444) WB Data: babebabe, to register:  2
+
+
+(80000454) Inst: 120213
+Decode: curr_pc: 80000450
+Writing 0000000b to  2
+(80000448) WB Data: babebabe, to register:  1
+
+
+(80000458) Inst: 200293
+Decode: curr_pc: 80000454
+Writing 0000000e to  1
+(8000044c) WB Data: babebabe, to register:  0
+
+
+(8000045c) Inst: fe5214e3
+Decode: curr_pc: 80000458
+(80000450) WB Data: babebabe, to register:  3
+
+
+(80000460) Inst: 300e93
+Decode: curr_pc: 8000045c
+Writing 00000003 to  3
+(80000454) WB Data: babebabe, to register:  4
+
+
+(80000460) Inst: 300e93
+Decode: curr_pc: 80000460
+Writing 00000002 to  4
+(80000458) WB Data: babebabe, to register:  5
+
+
+(80000460) Inst: 300e93
+Decode: curr_pc: 80000460
+Writing 00000002 to  5
+
+
+(80000464) Inst: 1d00e13
+Decode: curr_pc: 80000460
+
+
+(80000468) Inst: 11d19a63
+Decode: curr_pc: 80000464
+
+
+(8000046c) Inst: 213
+Decode: curr_pc: 80000468
+(80000460) WB Data: babebabe, to register: 29
+
+
+(8000046c) Inst: 213
+Decode: curr_pc: 8000046c
+Writing 00000003 to 29
+(80000464) WB Data: babebabe, to register: 28
+
+
+(8000046c) Inst: 213
+Decode: curr_pc: 8000046c
+Writing 0000001d to 28
+
+
+(80000470) Inst: b00113
+Decode: curr_pc: 8000046c
+
+
+(80000474) Inst: f00093
+Decode: curr_pc: 80000470
+
+
+(80000478) Inst: 13
+Decode: curr_pc: 80000474
+(8000046c) WB Data: babebabe, to register:  4
+
+
+(8000047c) Inst: 13
+Decode: curr_pc: 80000478
+Writing 00000000 to  4
+(80000470) WB Data: babebabe, to register:  2
+
+
+(80000480) Inst: 402081b3
+Decode: curr_pc: 8000047c
+Writing 0000000b to  2
+(80000474) WB Data: babebabe, to register:  1
+
+
+(80000484) Inst: 120213
+Decode: curr_pc: 80000480
+Writing 0000000f to  1
+(80000478) WB Data: babebabe, to register:  0
+
+
+(80000488) Inst: 200293
+Decode: curr_pc: 80000484
+(8000047c) WB Data: babebabe, to register:  0
+
+
+(8000048c) Inst: fe5212e3
+Decode: curr_pc: 80000488
+(80000480) WB Data: babebabe, to register:  3
+
+
+(80000490) Inst: 400e93
+Decode: curr_pc: 8000048c
+Writing 00000004 to  3
+(80000484) WB Data: babebabe, to register:  4
+
+
+(80000490) Inst: 400e93
+Decode: curr_pc: 80000490
+Writing 00000001 to  4
+(80000488) WB Data: babebabe, to register:  5
+
+
+(80000470) Inst: b00113
+Decode: curr_pc: 80000490
+Writing 00000002 to  5
+
+
+(80000474) Inst: f00093
+Decode: curr_pc: 80000470
+
+
+(80000478) Inst: 13
+Decode: curr_pc: 80000474
+
+
+(8000047c) Inst: 13
+Decode: curr_pc: 80000478
+(80000470) WB Data: babebabe, to register:  2
+
+
+(80000480) Inst: 402081b3
+Decode: curr_pc: 8000047c
+Writing 0000000b to  2
+(80000474) WB Data: babebabe, to register:  1
+
+
+(80000484) Inst: 120213
+Decode: curr_pc: 80000480
+Writing 0000000f to  1
+(80000478) WB Data: babebabe, to register:  0
+
+
+(80000488) Inst: 200293
+Decode: curr_pc: 80000484
+(8000047c) WB Data: babebabe, to register:  0
+
+
+(8000048c) Inst: fe5212e3
+Decode: curr_pc: 80000488
+(80000480) WB Data: babebabe, to register:  3
+
+
+(80000490) Inst: 400e93
+Decode: curr_pc: 8000048c
+Writing 00000004 to  3
+(80000484) WB Data: babebabe, to register:  4
+
+
+(80000490) Inst: 400e93
+Decode: curr_pc: 80000490
+Writing 00000002 to  4
+(80000488) WB Data: babebabe, to register:  5
+
+
+(80000490) Inst: 400e93
+Decode: curr_pc: 80000490
+Writing 00000002 to  5
+
+
+(80000494) Inst: 1e00e13
+Decode: curr_pc: 80000490
+
+
+(80000498) Inst: fd19263
+Decode: curr_pc: 80000494
+
+
+(8000049c) Inst: 213
+Decode: curr_pc: 80000498
+(80000490) WB Data: babebabe, to register: 29
+
+
+(8000049c) Inst: 213
+Decode: curr_pc: 8000049c
+Writing 00000004 to 29
+(80000494) WB Data: babebabe, to register: 28
+
+
+(8000049c) Inst: 213
+Decode: curr_pc: 8000049c
+Writing 0000001e to 28
+
+
+(800004a0) Inst: b00113
+Decode: curr_pc: 8000049c
+
+
+(800004a4) Inst: 13
+Decode: curr_pc: 800004a0
+
+
+(800004a8) Inst: d00093
+Decode: curr_pc: 800004a4
+(8000049c) WB Data: babebabe, to register:  4
+
+
+(800004ac) Inst: 402081b3
+Decode: curr_pc: 800004a8
+Writing 00000000 to  4
+(800004a0) WB Data: babebabe, to register:  2
+
+
+(800004b0) Inst: 120213
+Decode: curr_pc: 800004ac
+Writing 0000000b to  2
+(800004a4) WB Data: babebabe, to register:  0
+
+
+(800004b4) Inst: 200293
+Decode: curr_pc: 800004b0
+(800004a8) WB Data: babebabe, to register:  1
+
+
+(800004b8) Inst: fe5214e3
+Decode: curr_pc: 800004b4
+Writing 0000000d to  1
+(800004ac) WB Data: babebabe, to register:  3
+
+
+(800004bc) Inst: 200e93
+Decode: curr_pc: 800004b8
+Writing 00000002 to  3
+(800004b0) WB Data: babebabe, to register:  4
+
+
+(800004bc) Inst: 200e93
+Decode: curr_pc: 800004bc
+Writing 00000001 to  4
+(800004b4) WB Data: babebabe, to register:  5
+
+
+(800004a0) Inst: b00113
+Decode: curr_pc: 800004bc
+Writing 00000002 to  5
+
+
+(800004a4) Inst: 13
+Decode: curr_pc: 800004a0
+
+
+(800004a8) Inst: d00093
+Decode: curr_pc: 800004a4
+
+
+(800004ac) Inst: 402081b3
+Decode: curr_pc: 800004a8
+(800004a0) WB Data: babebabe, to register:  2
+
+
+(800004b0) Inst: 120213
+Decode: curr_pc: 800004ac
+Writing 0000000b to  2
+(800004a4) WB Data: babebabe, to register:  0
+
+
+(800004b4) Inst: 200293
+Decode: curr_pc: 800004b0
+(800004a8) WB Data: babebabe, to register:  1
+
+
+(800004b8) Inst: fe5214e3
+Decode: curr_pc: 800004b4
+Writing 0000000d to  1
+(800004ac) WB Data: babebabe, to register:  3
+
+
+(800004bc) Inst: 200e93
+Decode: curr_pc: 800004b8
+Writing 00000002 to  3
+(800004b0) WB Data: babebabe, to register:  4
+
+
+(800004bc) Inst: 200e93
+Decode: curr_pc: 800004bc
+Writing 00000002 to  4
+(800004b4) WB Data: babebabe, to register:  5
+
+
+(800004bc) Inst: 200e93
+Decode: curr_pc: 800004bc
+Writing 00000002 to  5
+
+
+(800004c0) Inst: 1f00e13
+Decode: curr_pc: 800004bc
diff --git a/rtl/obj_dir/test_bench.d b/rtl/obj_dir/test_bench.d
index b918f78f..5a33d4da 100644
--- a/rtl/obj_dir/test_bench.d
+++ b/rtl/obj_dir/test_bench.d
@@ -1,4 +1,5 @@
 test_bench.o: ../test_bench.cpp ../test_bench.h ../VX_define.h ../ram.h \
-  VVortex.h \
-  /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.h \
-  /usr/local/Cellar/verilator/4.010/share/verilator/include/verilatedos.h
+ VVortex.h /usr/local/share/verilator/include/verilated_heavy.h \
+ /usr/local/share/verilator/include/verilated.h \
+ /usr/local/share/verilator/include/verilatedos.h \
+ /usr/local/share/verilator/include/verilated.h
diff --git a/rtl/obj_dir/test_bench.o b/rtl/obj_dir/test_bench.o
index 090e350b..0087a027 100644
Binary files a/rtl/obj_dir/test_bench.o and b/rtl/obj_dir/test_bench.o differ
diff --git a/rtl/obj_dir/verilated.d b/rtl/obj_dir/verilated.d
index 8fb42837..4f8241f8 100644
--- a/rtl/obj_dir/verilated.d
+++ b/rtl/obj_dir/verilated.d
@@ -1,9 +1,8 @@
-verilated.o: \
-  /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.cpp \
-  /usr/local/Cellar/verilator/4.010/share/verilator/include/verilatedos.h \
-  /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_imp.h \
-  /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.h \
-  /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_heavy.h \
-  /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_syms.h \
-  /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_sym_props.h \
-  /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_config.h
+verilated.o: /usr/local/share/verilator/include/verilated.cpp \
+ /usr/local/share/verilator/include/verilatedos.h \
+ /usr/local/share/verilator/include/verilated_imp.h \
+ /usr/local/share/verilator/include/verilated.h \
+ /usr/local/share/verilator/include/verilated_heavy.h \
+ /usr/local/share/verilator/include/verilated_syms.h \
+ /usr/local/share/verilator/include/verilated_sym_props.h \
+ /usr/local/share/verilator/include/verilated_config.h
diff --git a/rtl/obj_dir/verilated.o b/rtl/obj_dir/verilated.o
index 7edd40bb..021e7b7b 100644
Binary files a/rtl/obj_dir/verilated.o and b/rtl/obj_dir/verilated.o differ
diff --git a/rtl/results.txt b/rtl/results.txt
index e69de29b..cec694bc 100644
--- a/rtl/results.txt
+++ b/rtl/results.txt
@@ -0,0 +1,9 @@
+
+****************	../../emulator/riscv_tests/rv32ui-p-sub.hex	****************
+# Dynamic Instructions: 496
+# of total cycles:      500
+# of forwarding stalls: 0
+# of branch stalls:     0
+# CPI:                  1.00806
+# time to simulate:     2.13149e-317 milliseconds
+# GRADE:                Failed on test: 4294967295
diff --git a/rtl/test_bench.cpp b/rtl/test_bench.cpp
index be70a1f3..9400378d 100644
--- a/rtl/test_bench.cpp
+++ b/rtl/test_bench.cpp
@@ -12,77 +12,77 @@ int main(int argc, char **argv)
 
 	Vortex v;
 
-    bool passed = true;
-	std::string tests[NUM_TESTS] = {
-		"../../emulator/riscv_tests/rv32ui-p-add.hex",
-		"../../emulator/riscv_tests/rv32ui-p-addi.hex",
-		"../../emulator/riscv_tests/rv32ui-p-and.hex",
-		"../../emulator/riscv_tests/rv32ui-p-andi.hex",
-		"../../emulator/riscv_tests/rv32ui-p-auipc.hex",
-		"../../emulator/riscv_tests/rv32ui-p-beq.hex",
-		"../../emulator/riscv_tests/rv32ui-p-bge.hex",
-		"../../emulator/riscv_tests/rv32ui-p-bgeu.hex",
-		"../../emulator/riscv_tests/rv32ui-p-blt.hex",
-		"../../emulator/riscv_tests/rv32ui-p-bltu.hex",
-		"../../emulator/riscv_tests/rv32ui-p-bne.hex",
-		"../../emulator/riscv_tests/rv32ui-p-jal.hex",
-		"../../emulator/riscv_tests/rv32ui-p-jalr.hex",
-		"../../emulator/riscv_tests/rv32ui-p-lb.hex",
-		"../../emulator/riscv_tests/rv32ui-p-lbu.hex",
-		"../../emulator/riscv_tests/rv32ui-p-lh.hex",
-		"../../emulator/riscv_tests/rv32ui-p-lhu.hex",
-		"../../emulator/riscv_tests/rv32ui-p-lui.hex",
-		"../../emulator/riscv_tests/rv32ui-p-lw.hex",
-		"../../emulator/riscv_tests/rv32ui-p-or.hex",
-		"../../emulator/riscv_tests/rv32ui-p-ori.hex",
-		"../../emulator/riscv_tests/rv32ui-p-sb.hex",
-		"../../emulator/riscv_tests/rv32ui-p-sh.hex",
-		"../../emulator/riscv_tests/rv32ui-p-simple.hex",
-		"../../emulator/riscv_tests/rv32ui-p-sll.hex",
-		"../../emulator/riscv_tests/rv32ui-p-slli.hex",
-		"../../emulator/riscv_tests/rv32ui-p-slt.hex",
-		"../../emulator/riscv_tests/rv32ui-p-slti.hex",
-		"../../emulator/riscv_tests/rv32ui-p-sltiu.hex",
-		"../../emulator/riscv_tests/rv32ui-p-sltu.hex",
-		"../../emulator/riscv_tests/rv32ui-p-sra.hex",
-		"../../emulator/riscv_tests/rv32ui-p-srai.hex",
-		"../../emulator/riscv_tests/rv32ui-p-srl.hex",
-		"../../emulator/riscv_tests/rv32ui-p-srli.hex",
-		"../../emulator/riscv_tests/rv32ui-p-sub.hex",
-		"../../emulator/riscv_tests/rv32ui-p-sw.hex",
-		"../../emulator/riscv_tests/rv32ui-p-xor.hex",
-		"../../emulator/riscv_tests/rv32ui-p-xori.hex",
-		"../../emulator/riscv_tests/rv32um-p-div.hex",
-		"../../emulator/riscv_tests/rv32um-p-divu.hex",
-		"../../emulator/riscv_tests/rv32um-p-mul.hex",
-		"../../emulator/riscv_tests/rv32um-p-mulh.hex",
-		"../../emulator/riscv_tests/rv32um-p-mulhsu.hex",
-		"../../emulator/riscv_tests/rv32um-p-mulhu.hex",
-		"../../emulator/riscv_tests/rv32um-p-rem.hex",
-		"../../emulator/riscv_tests/rv32um-p-remu.hex"
-	};
+ //    bool passed = true;
+	// std::string tests[NUM_TESTS] = {
+	// 	"../../emulator/riscv_tests/rv32ui-p-add.hex",
+	// 	"../../emulator/riscv_tests/rv32ui-p-addi.hex",
+	// 	"../../emulator/riscv_tests/rv32ui-p-and.hex",
+	// 	"../../emulator/riscv_tests/rv32ui-p-andi.hex",
+	// 	"../../emulator/riscv_tests/rv32ui-p-auipc.hex",
+	// 	"../../emulator/riscv_tests/rv32ui-p-beq.hex",
+	// 	"../../emulator/riscv_tests/rv32ui-p-bge.hex",
+	// 	"../../emulator/riscv_tests/rv32ui-p-bgeu.hex",
+	// 	"../../emulator/riscv_tests/rv32ui-p-blt.hex",
+	// 	"../../emulator/riscv_tests/rv32ui-p-bltu.hex",
+	// 	"../../emulator/riscv_tests/rv32ui-p-bne.hex",
+	// 	"../../emulator/riscv_tests/rv32ui-p-jal.hex",
+	// 	"../../emulator/riscv_tests/rv32ui-p-jalr.hex",
+	// 	"../../emulator/riscv_tests/rv32ui-p-lb.hex",
+	// 	"../../emulator/riscv_tests/rv32ui-p-lbu.hex",
+	// 	"../../emulator/riscv_tests/rv32ui-p-lh.hex",
+	// 	"../../emulator/riscv_tests/rv32ui-p-lhu.hex",
+	// 	"../../emulator/riscv_tests/rv32ui-p-lui.hex",
+	// 	"../../emulator/riscv_tests/rv32ui-p-lw.hex",
+	// 	"../../emulator/riscv_tests/rv32ui-p-or.hex",
+	// 	"../../emulator/riscv_tests/rv32ui-p-ori.hex",
+	// 	"../../emulator/riscv_tests/rv32ui-p-sb.hex",
+	// 	"../../emulator/riscv_tests/rv32ui-p-sh.hex",
+	// 	"../../emulator/riscv_tests/rv32ui-p-simple.hex",
+	// 	"../../emulator/riscv_tests/rv32ui-p-sll.hex",
+	// 	"../../emulator/riscv_tests/rv32ui-p-slli.hex",
+	// 	"../../emulator/riscv_tests/rv32ui-p-slt.hex",
+	// 	"../../emulator/riscv_tests/rv32ui-p-slti.hex",
+	// 	"../../emulator/riscv_tests/rv32ui-p-sltiu.hex",
+	// 	"../../emulator/riscv_tests/rv32ui-p-sltu.hex",
+	// 	"../../emulator/riscv_tests/rv32ui-p-sra.hex",
+	// 	"../../emulator/riscv_tests/rv32ui-p-srai.hex",
+	// 	"../../emulator/riscv_tests/rv32ui-p-srl.hex",
+	// 	"../../emulator/riscv_tests/rv32ui-p-srli.hex",
+	// 	"../../emulator/riscv_tests/rv32ui-p-sub.hex",
+	// 	"../../emulator/riscv_tests/rv32ui-p-sw.hex",
+	// 	"../../emulator/riscv_tests/rv32ui-p-xor.hex",
+	// 	"../../emulator/riscv_tests/rv32ui-p-xori.hex",
+	// 	"../../emulator/riscv_tests/rv32um-p-div.hex",
+	// 	"../../emulator/riscv_tests/rv32um-p-divu.hex",
+	// 	"../../emulator/riscv_tests/rv32um-p-mul.hex",
+	// 	"../../emulator/riscv_tests/rv32um-p-mulh.hex",
+	// 	"../../emulator/riscv_tests/rv32um-p-mulhsu.hex",
+	// 	"../../emulator/riscv_tests/rv32um-p-mulhu.hex",
+	// 	"../../emulator/riscv_tests/rv32um-p-rem.hex",
+	// 	"../../emulator/riscv_tests/rv32um-p-remu.hex"
+	// };
 
-		for (int ii = 0; ii < NUM_TESTS; ii++)
-		// for (int ii = 0; ii < NUM_TESTS - 1; ii++)
-		{
-			bool curr = v.simulate(tests[ii]);
+	// 	for (int ii = 0; ii < NUM_TESTS; ii++)
+	// 	// for (int ii = 0; ii < NUM_TESTS - 1; ii++)
+	// 	{
+	// 		bool curr = v.simulate(tests[ii]);
 
-			if ( curr) std::cerr << GREEN << "Test Passed: " << tests[ii] << std::endl;
-			if (!curr) std::cerr << RED   << "Test Failed: " << tests[ii] << std::endl;
-			passed = passed && curr;
+	// 		if ( curr) std::cerr << GREEN << "Test Passed: " << tests[ii] << std::endl;
+	// 		if (!curr) std::cerr << RED   << "Test Failed: " << tests[ii] << std::endl;
+	// 		passed = passed && curr;
 
-			std::cerr << DEFAULT;
-		}
+	// 		std::cerr << DEFAULT;
+	// 	}
 
-		if( passed) std::cerr << DEFAULT << "PASSED ALL TESTS\n";
-		if(!passed) std::cerr << DEFAULT << "Failed one or more tests\n";
+	// 	if( passed) std::cerr << DEFAULT << "PASSED ALL TESTS\n";
+	// 	if(!passed) std::cerr << DEFAULT << "Failed one or more tests\n";
 
 
-	// char testing[] = "../../src/riscv_tests/rv32ui-p-lw.hex";
+	char testing[] = "../../emulator/riscv_tests/rv32ui-p-sub.hex";
 
-	// bool curr = v.simulate(testing);
-	// if ( curr) std::cerr << GREEN << "Test Passed: " << testing << std::endl;
-	// if (!curr) std::cerr << RED   << "Test Failed: " << testing << std::endl;
+	bool curr = v.simulate(testing);
+	if ( curr) std::cerr << GREEN << "Test Passed: " << testing << std::endl;
+	if (!curr) std::cerr << RED   << "Test Failed: " << testing << std::endl;
 
 	return 0;
 
diff --git a/rtl/test_bench.h b/rtl/test_bench.h
index 48f133bc..4f1d5798 100644
--- a/rtl/test_bench.h
+++ b/rtl/test_bench.h
@@ -142,6 +142,8 @@ bool Vortex::ibus_driver()
     ram.getWord(new_PC, &curr_inst);
     vortex->fe_instruction      = curr_inst;
 
+    printf("\n\n(%x) Inst: %x\n", new_PC, curr_inst);
+
     ////////////////////// IBUS //////////////////////
 
 
@@ -284,20 +286,49 @@ bool Vortex::simulate(std::string file_to_simulate)
 	unsigned new_PC;
 
 	int cycle = 0;
-	while (this->stop && (!(stop && (counter > 5))))
-	{
+	// while (this->stop && (!(stop && (counter > 5))))
+	// {
 
-		// std::cout << "************* Cycle: " << cycle << "\n";
+	// 	// std::cout << "************* Cycle: " << cycle << "\n";
+ //        bool istop =  ibus_driver();
+ //        bool dstop = !dbus_driver();
+
+	// 	vortex->clk = 1;
+	// 	vortex->eval();
+
+
+
+	// 	vortex->clk = 0;
+	// 	vortex->eval();
+
+
+ //        stop = istop && dstop;
+
+ //        if (stop)
+ //        {
+ //            counter++;
+ //        } else
+ //        {
+ //            counter = 0;
+ //        }
+
+ //        cycle++;
+	// }
+
+    for (int i = 0; i < 500; i++)
+    {
+
+        // std::cout << "************* Cycle: " << cycle << "\n";
         bool istop =  ibus_driver();
         bool dstop = !dbus_driver();
 
-		vortex->clk = 1;
-		vortex->eval();
+        vortex->clk = 1;
+        vortex->eval();
 
 
 
-		vortex->clk = 0;
-		vortex->eval();
+        vortex->clk = 0;
+        vortex->eval();
 
 
         stop = istop && dstop;
@@ -311,7 +342,8 @@ bool Vortex::simulate(std::string file_to_simulate)
         }
 
         cycle++;
-	}
+    }
+
 
     uint32_t status;
     ram.getWord(0, &status);