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minor update

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This commit is contained in:
Blaise Tine
2020-05-21 13:42:08 -04:00
parent d12c40131e
commit cf22ef2bf3
16 changed files with 82 additions and 92 deletions
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19
hw/rtl/libs/VX_divide.v
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@@ -27,9 +27,7 @@ module VX_divide #(
generate
if (NREP != DREP) begin
`IGNORE_WARNINGS_BEGIN
different_nrep_drep_not_yet_supported non_existing_module();
`IGNORE_WARNINGS_END
end
if (IMPL == "quartus") begin
@@ -58,6 +56,7 @@ module VX_divide #(
wire [WIDTHN-1:0] numer_pipe_end;
wire [WIDTHD-1:0] denom_pipe_end;
if (PIPELINE == 0) begin
assign numer_pipe_end = numer;
assign denom_pipe_end = denom;
@@ -100,16 +99,6 @@ module VX_divide #(
if (NREP == "SIGNED") begin
/*VX_divide_ifnal_signed #(
.WIDTHN,
.WIDTHD
)div(
.numer(numer_pipe_end),
.denom(denom_pipe_end),
.quotient,
.remainder
);*/
always @(*) begin
if (denom_pipe_end == 0) begin
quotient = 32'hffffffff;
@@ -118,12 +107,12 @@ module VX_divide #(
else if (denom_pipe_end == 32'hffffffff && numer_pipe_end == 32'h80000000) begin
// this edge case kills verilator in some cases by causing a division
// overflow exception. INT_MIN / -1 (on x86)
quotient = 0;
quotient = 0;
remainder = 0;
end
else begin
quotient = $signed($signed(numer_pipe_end)/$signed(denom_pipe_end));
remainder = $signed($signed(numer_pipe_end)%$signed(denom_pipe_end));
quotient = $signed($signed(numer_pipe_end) / $signed(denom_pipe_end));
remainder = $signed($signed(numer_pipe_end) % $signed(denom_pipe_end));
end
end

18
hw/rtl/libs/VX_generic_queue.v
View File

@@ -4,26 +4,30 @@ module VX_generic_queue #(
parameter DATAW,
parameter SIZE = 16,
parameter BUFFERED_OUTPUT = 1
) (
`IGNORE_WARNINGS_BEGIN
) (
input wire clk,
input wire reset,
input wire push,
input wire pop,
output wire empty,
output wire full,
`IGNORE_WARNINGS_END
input wire pop,
input wire [DATAW-1:0] data_in,
output wire [DATAW-1:0] data_out,
output wire empty,
output wire full,
output wire [`LOG2UP(SIZE+1)-1:0] size
);
if (SIZE == 0) begin
assign empty = 1;
assign data_out = data_in;
assign data_out = 0;
assign full = 0;
assign size = 0;
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
`UNUSED_VAR (push)
`UNUSED_VAR (pop)
`UNUSED_VAR (data_in)
end else begin // (SIZE > 0)
`ifdef QUEUE_FORCE_MLAB

28
hw/rtl/libs/VX_generic_register.v
View File

@@ -4,33 +4,25 @@ module VX_generic_register #(
parameter N,
parameter PassThru = 0
) (
`IGNORE_WARNINGS_BEGIN
input wire clk,
input wire reset,
input wire stall,
input wire flush,
`IGNORE_WARNINGS_END
input wire[N-1:0] in,
output wire[N-1:0] out
);
reg [(N-1):0] value;
if (PassThru) begin
assign out = in;
end else begin
reg [(N-1):0] value;
always @(posedge clk) begin
if (reset) begin
value <= 0;
end else if (flush) begin
value <= 0;
end else if (~stall) begin
value <= in;
end
always @(posedge clk) begin
if (reset) begin
value <= 0;
end else if (flush) begin
value <= 0;
end else if (~stall) begin
value <= in;
end
assign out = value;
end
assign out = PassThru ? in : value;
endmodule

3
hw/rtl/libs/VX_mult.v
View File

@@ -34,7 +34,6 @@ module VX_mult #(
localparam lpm_speed = (SPEED == "HIGHEST") ? 10 : 5;
if (FORCE_LE == "YES") begin
`IGNORE_WARNINGS_BEGIN
lpm_mult #(
.LPM_WIDTHA(WIDTHA),
.LPM_WIDTHB(WIDTHB),
@@ -51,7 +50,6 @@ module VX_mult #(
.datab(datab),
.result(result)
);
`IGNORE_WARNINGS_END
end
else begin
lpm_mult#(
@@ -76,6 +74,7 @@ module VX_mult #(
wire [WIDTHA-1:0] dataa_pipe_end;
wire [WIDTHB-1:0] datab_pipe_end;
if (PIPELINE == 0) begin
assign dataa_pipe_end = dataa;
assign datab_pipe_end = datab;