minor update
This commit is contained in:
10
hw/rtl/cache/VX_bank.v
vendored
10
hw/rtl/cache/VX_bank.v
vendored
@@ -113,7 +113,6 @@ module VX_bank #(
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wire[2:0] debug_mem_write_st0;
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wire[`REQS_BITS-1:0] debug_tid_st0;
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wire[31:0] debug_use_pc_st1e;
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wire[1:0] debug_wb_st1e;
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wire[4:0] debug_rd_st1e;
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@@ -122,7 +121,6 @@ module VX_bank #(
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wire[2:0] debug_mem_write_st1e;
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wire[`REQS_BITS-1:0] debug_tid_st1e;
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wire[31:0] debug_use_pc_st2;
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wire[1:0] debug_wb_st2;
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wire[4:0] debug_rd_st2;
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@@ -151,7 +149,7 @@ module VX_bank #(
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.data_out({snrq_addr_st0, snrq_tag_st0}),
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.empty (snrq_empty),
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.full (snrq_full),
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`UNUSED_PIN(size)
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`UNUSED_PIN (size)
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);
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assign snp_req_ready = ~snrq_full;
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@@ -174,7 +172,7 @@ module VX_bank #(
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.data_out({dfpq_addr_st0, dfpq_filldata_st0}),
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.empty (dfpq_empty),
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.full (dfpq_full),
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`UNUSED_PIN(size)
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`UNUSED_PIN (size)
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);
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assign dram_fill_rsp_ready = !dfpq_full;
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@@ -585,7 +583,7 @@ module VX_bank #(
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.data_out({core_rsp_tid, core_rsp_tag, core_rsp_data}),
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.empty (cwbq_empty),
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.full (cwbq_full),
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`UNUSED_PIN(size)
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`UNUSED_PIN (size)
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);
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assign core_rsp_valid = !cwbq_empty;
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@@ -655,7 +653,7 @@ module VX_bank #(
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.data_out({dwbq_is_dwb_out, dwbq_is_snp_out, dram_wb_req_addr, dram_wb_req_data, snp_rsp_tag}),
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.empty (dwbq_empty),
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.full (dwbq_full),
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`UNUSED_PIN(size)
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`UNUSED_PIN (size)
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);
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wire dram_wb_req_fire = dram_wb_req_valid && dram_wb_req_ready;
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