Mrvq stopping reqq popping added to avoid mrvq full deadlock
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@@ -218,6 +218,7 @@ module VX_bank
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wire mrvq_pop;
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wire mrvq_full;
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wire mrvq_stop;
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wire mrvq_valid_st0;
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wire[`vx_clog2(NUMBER_REQUESTS)-1:0] mrvq_tid_st0;
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wire [31:0] mrvq_addr_st0;
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@@ -279,6 +280,7 @@ module VX_bank
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.miss_add_mem_write (miss_add_mem_write),
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.miss_add_pc (miss_add_pc),
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.miss_resrv_full (mrvq_full),
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.miss_resrv_stop (mrvq_stop),
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// Broadcast
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.is_fill_st1 (is_fill_st2),
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@@ -321,7 +323,7 @@ module VX_bank
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assign mrvq_pop = mrvq_valid_st0 && !stall_bank_pipe && !mrvq_hazard_st0;
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assign dfpq_pop = !mrvq_pop && !dfpq_empty && !stall_bank_pipe && !dfpq_hazard_st0;
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assign reqq_pop = !mrvq_pop && !dfpq_pop && !reqq_empty && reqq_req_st0 && !stall_bank_pipe && !is_fill_st1[0] && !(reqq_hazard_st0 || (mrvq_valid_st0 && mrvq_hazard_st0)) && !is_fill_in_pipe;
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assign reqq_pop = !mrvq_stop && !mrvq_pop && !dfpq_pop && !reqq_empty && reqq_req_st0 && !stall_bank_pipe && !is_fill_st1[0] && !(reqq_hazard_st0 || (mrvq_valid_st0 && mrvq_hazard_st0)) && !is_fill_in_pipe;
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assign snrq_pop = !reqq_pop && !reqq_pop && !mrvq_pop && !dfpq_pop && snrq_valid_st0 && !stall_bank_pipe && !snrq_hazard_st0;
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integer st1_cycle;
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