multicore fix
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@@ -8,8 +8,8 @@ double sc_time_stamp() {
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return time_stamp;
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}
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Simulator::Simulator(RAM *ram) {
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ram_ = ram;
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Simulator::Simulator() {
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ram_ = nullptr;
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vortex_ = new VVortex_Socket();
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#ifdef VCD_OUTPUT
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@@ -27,12 +27,20 @@ Simulator::~Simulator() {
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delete vortex_;
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}
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void Simulator::attach_ram(RAM* ram) {
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ram_ = ram;
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dram_rsp_vec_.clear();
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}
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void Simulator::print_stats(std::ostream& out) {
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out << std::left;
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out << std::setw(24) << "# of total cycles:" << std::dec << time_stamp/2 << std::endl;
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}
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void Simulator::dbus_driver() {
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if (ram_ == nullptr)
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return;
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// handle DRAM response cycle
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int dequeue_index = -1;
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for (int i = 0; i < dram_rsp_vec_.size(); i++) {
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@@ -149,9 +157,6 @@ bool Simulator::is_busy() {
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}
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void Simulator::flush_caches(uint32_t mem_addr, uint32_t size) {
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// send snoop requests to the caches
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printf("[sim] total cycles: %ld\n", time_stamp/2);
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// align address to LLC block boundaries
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auto aligned_addr_start = mem_addr / GLOBAL_BLOCK_SIZE;
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auto aligned_addr_end = (mem_addr + size + GLOBAL_BLOCK_SIZE - 1) / GLOBAL_BLOCK_SIZE;
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@@ -29,7 +29,7 @@ typedef struct {
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class Simulator {
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public:
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Simulator(RAM *ram);
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Simulator();
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virtual ~Simulator();
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bool is_busy();
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@@ -37,6 +37,9 @@ public:
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void step();
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void wait(uint32_t cycles);
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void flush_caches(uint32_t mem_addr, uint32_t size);
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void attach_ram(RAM* ram);
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bool run();
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void print_stats(std::ostream& out);
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@@ -71,7 +71,8 @@ int main(int argc, char **argv)
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RAM ram;
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loadHexImpl(s.c_str(), &ram);
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Simulator simulator(&ram);
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Simulator simulator;
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simulator.attach_ram(&ram);
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bool curr = simulator.run();
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if (curr) std::cerr << GREEN << "Test Passed: " << s << std::endl;
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@@ -106,7 +107,8 @@ int main(int argc, char **argv)
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RAM ram;
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loadHexImpl(testing, &ram);
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Simulator simulator(&ram);
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Simulator simulator;
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simulator.attach_ram(&ram);
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bool curr = simulator.run();
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if (curr) std::cerr << GREEN << "Test Passed: " << testing << std::endl;
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