minor update
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@@ -306,7 +306,7 @@ module VX_lsu_unit #(
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`SCOPE_ASSIGN (dcache_rsp_tag, mbuf_raddr);
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`ifndef SYNTHESIS
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reg [`LSUQ_SIZE-1:0][(`NW_BITS + 32 + 64 + 1)-1:0] pending_reqs;
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reg [`LSUQ_SIZE-1:0][(`NW_BITS + 32 + `NR_BITS + 64 + 1)-1:0] pending_reqs;
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wire [63:0] delay_timeout = 10000 * (1 ** (`L2_ENABLE + `L3_ENABLE));
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always @(posedge clk) begin
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@@ -314,7 +314,7 @@ module VX_lsu_unit #(
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pending_reqs <= '0;
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end begin
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if (mbuf_push) begin
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pending_reqs[mbuf_waddr] <= {req_wid, req_pc, $time, 1'b1};
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pending_reqs[mbuf_waddr] <= {req_wid, req_pc, req_rd, $time, 1'b1};
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end
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if (mbuf_pop) begin
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pending_reqs[mbuf_raddr] <= '0;
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@@ -324,7 +324,8 @@ module VX_lsu_unit #(
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for (integer i = 0; i < `LSUQ_SIZE; ++i) begin
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if (pending_reqs[i][0]) begin
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assert(($time - pending_reqs[i][1 +: 64]) < delay_timeout) else
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$error("%t: *** D$%0d response timeout: wid=%0d, PC=%0h", $time, CORE_ID, pending_reqs[i][1+64+32 +: `NW_BITS], pending_reqs[i][1+64 +: 32]);
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$error("%t: *** D$%0d response timeout: remaining=%b, wid=%0d, PC=%0h, rd=%0d", $time, CORE_ID,
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rsp_rem_mask[i], pending_reqs[i][1+64+32+`NR_BITS +: `NW_BITS], pending_reqs[i][1+64+`NR_BITS +: 32], pending_reqs[i][1+64 +: `NR_BITS]);
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end
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end
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end
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