L3 and CLUSTRING WORKS
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@@ -7,10 +7,12 @@ module VX_dmem_controller (
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// Dram <-> Dcache
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VX_gpu_dcache_dram_req_inter VX_gpu_dcache_dram_req,
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VX_gpu_dcache_dram_res_inter VX_gpu_dcache_dram_res,
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VX_gpu_snp_req_rsp VX_gpu_dcache_snp_req,
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// Dram <-> Icache
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VX_gpu_dcache_dram_req_inter VX_gpu_icache_dram_req,
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VX_gpu_dcache_dram_res_inter VX_gpu_icache_dram_res,
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VX_gpu_snp_req_rsp VX_gpu_icache_snp_req,
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// Core <-> Dcache
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VX_gpu_dcache_res_inter VX_dcache_rsp,
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@@ -149,7 +151,12 @@ module VX_dmem_controller (
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// Snoop Request
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.snp_req (0),
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.snp_req_addr (0)
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.snp_req_addr (0),
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// Snoop Forward
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.snp_fwd (),
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.snp_fwd_addr (),
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.snp_fwd_delay (0)
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);
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VX_cache #(
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@@ -224,8 +231,15 @@ module VX_dmem_controller (
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.dram_snp_full (VX_gpu_dcache_dram_req.dram_snp_full),
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// Snoop Request
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.snp_req (0),
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.snp_req_addr (0)
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.snp_req (VX_gpu_dcache_snp_req.snp_req),
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.snp_req_addr (VX_gpu_dcache_snp_req.snp_req_addr),
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.snp_req_delay (VX_gpu_dcache_snp_req.snp_delay),
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// Snoop Forward
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.snp_fwd (),
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.snp_fwd_addr (),
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.snp_fwd_delay (0)
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);
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@@ -301,9 +315,16 @@ module VX_dmem_controller (
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.dram_req_because_of_wb(VX_gpu_icache_dram_req.dram_because_of_snp),
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.dram_snp_full (VX_gpu_icache_dram_req.dram_snp_full),
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// Snoop Request
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.snp_req (0),
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.snp_req_addr (0)
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.snp_req (VX_gpu_icache_snp_req.snp_req),
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.snp_req_addr (VX_gpu_icache_snp_req.snp_req_addr),
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.snp_req_delay (VX_gpu_icache_snp_req.snp_delay),
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// Snoop Forward
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.snp_fwd (),
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.snp_fwd_addr (),
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.snp_fwd_delay (0)
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);
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