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L3 and CLUSTRING WORKS

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This commit is contained in:
felsabbagh3
2020-03-10 02:41:47 -07:00
parent dea271eb6b
commit ca62e57a0d
11 changed files with 654 additions and 262 deletions
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29
rtl/VX_cache/VX_bank.v
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@@ -98,9 +98,11 @@ module VX_bank
// Snp Request
input wire snp_req,
input wire[31:0] snp_req_addr,
output wire snrq_full,
output wire snp_fwd,
output wire[31:0] snp_fwd_addr
output wire[31:0] snp_fwd_addr,
input wire snp_fwd_pop
);
@@ -108,7 +110,6 @@ module VX_bank
wire snrq_pop;
wire snrq_empty;
wire snrq_full;
wire snrq_valid_st0;
wire[31:0] snrq_addr_st0;
@@ -516,7 +517,7 @@ module VX_bank
// Enqueue to miss reserv if it's a valid miss
assign miss_add = valid_st2 && miss_st2 && !mrvq_full && !(((valid_st2 && !miss_st2) && cwbq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full));
assign miss_add = valid_st2 && miss_st2 && !mrvq_full && !((is_snp_st2 && valid_st2 && ffsq_full) ||((valid_st2 && !miss_st2) && cwbq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full));
assign miss_add_pc = pc_st2;
assign miss_add_addr = addr_st2;
assign miss_add_data = writeword_st2;
@@ -524,7 +525,7 @@ module VX_bank
// Enqueue to CWB Queue
wire cwbq_push = (valid_st2 && !miss_st2) && !cwbq_full && !((FUNC_ID == `LLFUNC_ID) && (miss_add_wb == 0)) && !( (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full));
wire cwbq_push = (valid_st2 && !miss_st2) && !cwbq_full && !((FUNC_ID == `LLFUNC_ID) && (miss_add_wb == 0)) && !((is_snp_st2 && valid_st2 && ffsq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full));
wire [`WORD_SIZE_RNG] cwbq_data = readword_st2;
wire [`vx_clog2(NUMBER_REQUESTS)-1:0] cwbq_tid = miss_add_tid;
wire [4:0] cwbq_rd = miss_add_rd;
@@ -549,7 +550,7 @@ module VX_bank
);
// Enqueue to DWB Queue
wire dwbq_push = ((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && !dwbq_full && !(((valid_st2 && !miss_st2) && cwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full));
wire dwbq_push = ((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && !dwbq_full && !((is_snp_st2 && valid_st2 && ffsq_full) ||((valid_st2 && !miss_st2) && cwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full));
wire[31:0] dwbq_req_addr = {readtag_st2, addr_st2[`LINE_SELECT_ADDR_END:0]} & `BASE_ADDR_MASK;
wire[`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] dwbq_req_data = readdata_st2;
wire dwbq_empty;
@@ -609,11 +610,25 @@ module VX_bank
);
wire snp_fwd_push;
wire snp_fwd_pop;
wire ffsq_full;
wire ffsq_empty;
assign snp_fwd_push = is_snp_st2 && valid_st2 && !ffsq_full && !(((valid_st2 && !miss_st2) && cwbq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full));
assign snp_fwd = !ffsq_empty;
VX_generic_queue_ll #(.DATAW(32), .SIZE(FFSQ_SIZE)) ffs_queue(
.clk (clk),
.reset (reset),
.push (snp_fwd_push),
.in_data ({addr_st2}),
.pop (snp_fwd_pop),
.out_data({snp_fwd_addr}),
.empty (ffsq_empty),
.full (ffsq_full)
);
assign stall_bank_pipe = ((valid_st2 && !miss_st2) && cwbq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full);
assign stall_bank_pipe = (is_snp_st2 && valid_st2 && ffsq_full) || ((valid_st2 && !miss_st2) && cwbq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full);
endmodule

57
rtl/VX_cache/VX_cache.v
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@@ -96,7 +96,13 @@ module VX_cache
// Snoop Req
input wire snp_req,
input wire[31:0] snp_req_addr
input wire[31:0] snp_req_addr,
output wire snp_req_delay,
// Snoop Forward
output wire snp_fwd,
output wire[31:0] snp_fwd_addr,
input wire snp_fwd_delay
);
@@ -126,9 +132,19 @@ module VX_cache
wire[NUMBER_BANKS-1:0] per_bank_reqq_full;
wire[NUMBER_BANKS-1:0] per_bank_snrq_full;
wire[NUMBER_BANKS-1:0] per_bank_snp_fwd;
wire[NUMBER_BANKS-1:0][31:0] per_bank_snp_fwd_addr;
wire[NUMBER_BANKS-1:0] per_bank_snp_fwd_pop;
assign delay_req = (|per_bank_reqq_full);
assign snp_req_delay = (|per_bank_snrq_full);
assign dram_fill_accept = (NUMBER_BANKS == 1) ? per_bank_dram_fill_accept[0] : per_bank_dram_fill_accept[dram_fill_rsp_addr[`BANK_SELECT_ADDR_RNG]];
VX_cache_dram_req_arb #(
@@ -238,6 +254,21 @@ module VX_cache
.core_wb_pc (core_wb_pc)
);
// Snoop Forward Logic
VX_snp_fwd_arb #(.NUMBER_BANKS(NUMBER_BANKS)) VX_snp_fwd_arb(
.per_bank_snp_fwd (per_bank_snp_fwd),
.per_bank_snp_fwd_addr(per_bank_snp_fwd_addr),
.per_bank_snp_fwd_pop (per_bank_snp_fwd_pop),
.snp_fwd (snp_fwd),
.snp_fwd_addr (snp_fwd_addr),
.snp_fwd_delay (snp_fwd_delay)
);
// Snoop Forward Logic
genvar curr_bank;
generate
for (curr_bank = 0; curr_bank < NUMBER_BANKS; curr_bank=curr_bank+1) begin
@@ -282,6 +313,11 @@ module VX_cache
wire curr_bank_reqq_full;
wire curr_bank_snp_fwd;
wire[31:0] curr_bank_snp_fwd_addr;
wire curr_bank_snp_fwd_pop;
wire curr_bank_snrq_full;
// Core Req
@@ -326,8 +362,15 @@ module VX_cache
assign per_bank_dram_wb_req_data[curr_bank] = curr_bank_dram_wb_req_data;
// Snoop Request
assign curr_bank_snp_req = snp_req && (snp_req_addr[`BANK_SELECT_ADDR_RNG] == curr_bank);
assign curr_bank_snp_req_addr = snp_req_addr;
assign curr_bank_snp_req = snp_req && (snp_req_addr[`BANK_SELECT_ADDR_RNG] == curr_bank);
assign curr_bank_snp_req_addr = snp_req_addr;
assign per_bank_snrq_full[curr_bank] = curr_bank_snrq_full;
// Snoop Fwd
assign curr_bank_snp_fwd_pop = per_bank_snp_fwd_pop[curr_bank];
assign per_bank_snp_fwd[curr_bank] = curr_bank_snp_fwd;
assign per_bank_snp_fwd_addr[curr_bank] = curr_bank_snp_fwd_addr;
VX_bank #(
.CACHE_SIZE_BYTES (CACHE_SIZE_BYTES),
@@ -398,7 +441,13 @@ module VX_cache
// Snoop Request
.snp_req (curr_bank_snp_req),
.snp_req_addr (curr_bank_snp_req_addr)
.snp_req_addr (curr_bank_snp_req_addr),
.snrq_full (curr_bank_snrq_full),
// Snoop Fwd
.snp_fwd (curr_bank_snp_fwd),
.snp_fwd_addr (curr_bank_snp_fwd_addr),
.snp_fwd_pop (curr_bank_snp_fwd_pop)
);

55
rtl/VX_cache/VX_cache_req_queue.v
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@@ -110,7 +110,7 @@ module VX_cache_req_queue
wire [NUMBER_REQUESTS-1:0][2:0] qual_mem_write;
wire [31:0] qual_pc;
wire[NUMBER_REQUESTS-1:0] updated_valids;
reg [NUMBER_REQUESTS-1:0] updated_valids;
wire o_empty;
@@ -118,7 +118,7 @@ module VX_cache_req_queue
wire out_empty = !(|out_per_valids) || o_empty;
wire push_qual = reqq_push && !reqq_full;
wire pop_qual = reqq_pop && use_empty && !out_empty;
wire pop_qual = !out_empty && use_empty;
VX_generic_queue_ll #(.DATAW( (NUMBER_REQUESTS * (1+32+`WORD_SIZE)) + 5 + (NUMBER_REQUESTS*2) + (`NW_M1+1) + (NUMBER_REQUESTS * (3 + 3)) + 32 ), .SIZE(REQQ_SIZE)) reqq_queue(
.clk (clk),
@@ -134,15 +134,15 @@ module VX_cache_req_queue
wire[NUMBER_REQUESTS-1:0] real_out_per_valids = out_per_valids & {NUMBER_REQUESTS{~out_empty}};
assign qual_valids = use_empty ? real_out_per_valids : out_empty ? 0 : use_per_valids;
assign qual_addr = use_empty ? out_per_addr : use_per_addr;
assign qual_writedata = use_empty ? out_per_writedata : use_per_writedata;
assign qual_rd = use_empty ? out_per_rd : use_per_rd;
assign qual_wb = use_empty ? out_per_wb : use_per_wb;
assign qual_warp_num = use_empty ? out_per_warp_num : use_per_warp_num;
assign qual_mem_read = use_empty ? out_per_mem_read : use_per_mem_read;
assign qual_mem_write = use_empty ? out_per_mem_write : use_per_mem_write;
assign qual_pc = use_empty ? out_per_pc : use_per_pc;
assign qual_valids = use_per_valids;
assign qual_addr = use_per_addr;
assign qual_writedata = use_per_writedata;
assign qual_rd = use_per_rd;
assign qual_wb = use_per_wb;
assign qual_warp_num = use_per_warp_num;
assign qual_mem_read = use_per_mem_read;
assign qual_mem_write = use_per_mem_write;
assign qual_pc = use_per_pc;
wire[`vx_clog2(NUMBER_REQUESTS)-1:0] qual_request_index;
wire qual_has_request;
@@ -164,7 +164,14 @@ module VX_cache_req_queue
assign reqq_req_mem_write_st0 = qual_mem_write[qual_request_index];
assign reqq_req_pc_st0 = qual_pc;
assign updated_valids = qual_valids & (~(1 << qual_request_index));
always @(*) begin
assign updated_valids = qual_valids;
if (qual_has_request) begin
assign updated_valids[qual_request_index] = 0;
end
end
always @(posedge clk) begin
if (reset) begin
@@ -178,17 +185,19 @@ module VX_cache_req_queue
use_per_mem_write <= 0;
use_per_pc <= 0;
end else begin
if (reqq_pop && qual_has_request) begin
use_per_valids <= updated_valids;
use_per_addr <= qual_addr;
use_per_writedata <= qual_writedata;
use_per_rd <= qual_rd;
use_per_wb <= qual_wb;
use_per_warp_num <= qual_warp_num;
use_per_mem_read <= qual_mem_read;
use_per_mem_write <= qual_mem_write;
use_per_pc <= qual_pc;
end
if (pop_qual) begin
use_per_valids <= real_out_per_valids;
use_per_addr <= out_per_addr;
use_per_writedata <= out_per_writedata;
use_per_rd <= out_per_rd;
use_per_wb <= out_per_wb;
use_per_warp_num <= out_per_warp_num;
use_per_mem_read <= out_per_mem_read;
use_per_mem_write <= out_per_mem_write;
use_per_pc <= out_per_pc;
end else if (reqq_pop) begin
use_per_valids[qual_request_index] <= 0;
end
// else if (reqq_pop) begin
// use_per_valids[qual_request_index] <= updated_valids;
// end

18
rtl/VX_cache/VX_cache_wb_sel_merge.v
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@@ -75,20 +75,20 @@ module VX_cache_wb_sel_merge
reg [NUMBER_BANKS-1:0] per_bank_wb_pop_unqual;
assign per_bank_wb_pop = per_bank_wb_pop_unqual & {NUMBER_BANKS{~core_no_wb_slot}};
wire[NUMBER_BANKS-1:0] bank_wants_wb;
genvar curr_bank;
generate
for (curr_bank = 0; curr_bank < NUMBER_BANKS; curr_bank=curr_bank+1) begin
assign bank_wants_wb[curr_bank] = (|per_bank_wb_valid[curr_bank]);
end
endgenerate
// wire[NUMBER_BANKS-1:0] bank_wants_wb;
// genvar curr_bank;
// generate
// for (curr_bank = 0; curr_bank < NUMBER_BANKS; curr_bank=curr_bank+1) begin
// assign bank_wants_wb[curr_bank] = (|per_bank_wb_valid[curr_bank]);
// end
// endgenerate
wire [(`vx_clog2(NUMBER_BANKS))-1:0] main_bank_index;
wire found_bank;
VX_generic_priority_encoder #(.N(NUMBER_BANKS)) VX_sel_bank(
.valids(bank_wants_wb),
.valids(per_bank_wb_valid),
.index (main_bank_index),
.found (found_bank)
);
@@ -105,7 +105,7 @@ module VX_cache_wb_sel_merge
core_wb_pc = 0;
core_wb_address = 0;
for (this_bank = 0; this_bank < NUMBER_BANKS; this_bank = this_bank + 1) begin
if (((FUNC_ID == `LLFUNC_ID) && found_bank && per_bank_wb_valid[this_bank]) || (found_bank && (per_bank_wb_valid[this_bank]) && (per_bank_wb_rd[this_bank] == per_bank_wb_rd[main_bank_index]) && (per_bank_wb_warp_num[this_bank] == per_bank_wb_warp_num[main_bank_index]))) begin
if (((FUNC_ID == `LLFUNC_ID) && found_bank && per_bank_wb_valid[this_bank] && ((this_bank == main_bank_index) || (per_bank_wb_tid[this_bank] != per_bank_wb_tid[main_bank_index]))) || ((FUNC_ID != `LLFUNC_ID) && ((this_bank == main_bank_index) || (per_bank_wb_tid[this_bank] != per_bank_wb_tid[main_bank_index])) && found_bank && (per_bank_wb_valid[this_bank]) && (per_bank_wb_rd[this_bank] == per_bank_wb_rd[main_bank_index]) && (per_bank_wb_warp_num[this_bank] == per_bank_wb_warp_num[main_bank_index]))) begin
core_wb_valid[per_bank_wb_tid[this_bank]] = 1;
core_wb_readdata[per_bank_wb_tid[this_bank]] = per_bank_wb_data[this_bank];
core_wb_pc[per_bank_wb_tid[this_bank]] = per_bank_wb_pc[this_bank];

39
rtl/VX_cache/VX_snp_fwd_arb.v Normal file
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@@ -0,0 +1,39 @@
module VX_snp_fwd_arb
#(
parameter NUMBER_BANKS = 8
)
(
input wire[NUMBER_BANKS-1:0] per_bank_snp_fwd,
input wire[NUMBER_BANKS-1:0][31:0] per_bank_snp_fwd_addr,
output reg[NUMBER_BANKS-1:0] per_bank_snp_fwd_pop,
output wire snp_fwd,
output wire[31:0] snp_fwd_addr,
input wire snp_fwd_delay
);
wire[NUMBER_BANKS-1:0] qual_per_bank_snp_fwd = per_bank_snp_fwd & {NUMBER_BANKS{!snp_fwd_delay}};
wire[`vx_clog2(NUMBER_BANKS)-1:0] fsq_bank;
wire fsq_valid;
VX_generic_priority_encoder #(.N(NUMBER_BANKS)) VX_sel_ffsq(
.valids(qual_per_bank_snp_fwd),
.index (fsq_bank),
.found (fsq_valid)
);
assign snp_fwd = fsq_valid;
assign snp_fwd_addr = per_bank_snp_fwd_addr[fsq_bank];
always @(*) begin
assign per_bank_snp_fwd_pop = 0;
if (fsq_valid) begin
per_bank_snp_fwd_pop[fsq_bank] = 1;
end
end
endmodule