OUTPUT_REG => OUT_REG renaming
This commit is contained in:
6
hw/rtl/cache/VX_bank.v
vendored
6
hw/rtl/cache/VX_bank.v
vendored
@@ -465,9 +465,9 @@ module VX_bank #(
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end
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VX_elastic_buffer #(
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.DATAW (NUM_PORTS * (CORE_TAG_WIDTH + 1 + `WORD_WIDTH + `REQS_BITS)),
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.SIZE (CRSQ_SIZE),
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.OUTPUT_REG (1 == NUM_BANKS)
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.DATAW (NUM_PORTS * (CORE_TAG_WIDTH + 1 + `WORD_WIDTH + `REQS_BITS)),
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.SIZE (CRSQ_SIZE),
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.OUT_REG (1 == NUM_BANKS)
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) core_rsp_req (
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.clk (clk),
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.reset (reset),
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6
hw/rtl/cache/VX_cache.v
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6
hw/rtl/cache/VX_cache.v
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@@ -314,9 +314,9 @@ module VX_cache #(
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`RESET_RELAY (mrsq_reset);
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VX_elastic_buffer #(
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.DATAW (MEM_TAG_IN_WIDTH + `CACHE_LINE_WIDTH),
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.SIZE (MRSQ_SIZE),
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.OUTPUT_REG (MRSQ_SIZE > 2)
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.DATAW (MEM_TAG_IN_WIDTH + `CACHE_LINE_WIDTH),
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.SIZE (MRSQ_SIZE),
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.OUT_REG (MRSQ_SIZE > 2)
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) mem_rsp_queue (
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.clk (clk),
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.reset (mrsq_reset),
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6
hw/rtl/cache/VX_shared_mem.v
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6
hw/rtl/cache/VX_shared_mem.v
vendored
@@ -127,9 +127,9 @@ module VX_shared_mem #(
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assign core_req_writeonly_unqual = ~(| core_req_read_mask_unqual);
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VX_elastic_buffer #(
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.DATAW (NUM_BANKS * (1 + 1 + `LINE_ADDR_WIDTH + WORD_SIZE + `WORD_WIDTH + CORE_TAG_WIDTH + `REQS_BITS) + NUM_BANKS + 1),
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.SIZE (CREQ_SIZE),
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.OUTPUT_REG (1) // output should be registered for the data_store addr port
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.DATAW (NUM_BANKS * (1 + 1 + `LINE_ADDR_WIDTH + WORD_SIZE + `WORD_WIDTH + CORE_TAG_WIDTH + `REQS_BITS) + NUM_BANKS + 1),
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.SIZE (CREQ_SIZE),
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.OUT_REG (1) // output should be registered for the data_store addr port
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) core_req_queue (
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.clk (clk),
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.reset (reset),
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