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cache bindings and memory perf refactory

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Blaise Tine
2023-11-03 08:18:18 -04:00
parent 69f9ae778d
commit c9e6518e05
20 changed files with 746 additions and 1025 deletions
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hw/rtl/core/VX_trace.vh
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@@ -358,9 +358,6 @@ task trace_ex_op(input int level,
`INST_SFU_CSRRW: begin if (use_imm) `TRACE(level, ("CSRRWI")); else `TRACE(level, ("CSRRW")); end
`INST_SFU_CSRRS: begin if (use_imm) `TRACE(level, ("CSRRSI")); else `TRACE(level, ("CSRRS")); end
`INST_SFU_CSRRC: begin if (use_imm) `TRACE(level, ("CSRRCI")); else `TRACE(level, ("CSRRC")); end
`INST_SFU_TEX: `TRACE(level, ("TEX"));
`INST_SFU_RASTER:`TRACE(level, ("RASTER"));
`INST_SFU_ROP: `TRACE(level, ("ROP"));
default: `TRACE(level, ("?"));
endcase
end