wu-arch/kernels
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

merge fixes

Browse Source
This commit is contained in:
Blaise Tine
2020-06-23 14:40:29 -07:00
parent d1103733f5
commit c9c34cb71a
9 changed files with 0 additions and 650 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
simX/include/archdef.h
View File

@@ -16,12 +16,7 @@ namespace Harp {
public:
struct Undefined {};
<<<<<<< HEAD
ArchDef(const std::string &s, bool cpu_mode = false)
: cpu_mode_(cpu_mode) {
=======
ArchDef(const std::string &s, int num_warps = 32, int num_threads = 32) {
>>>>>>> fpga_synthesis
std::istringstream iss(s.c_str());
wordSize = 4;

100
simX/instruction.cpp
View File

@@ -707,105 +707,6 @@ void Instruction::executeOn(Warp &c, trace_inst_t *trace_inst) {
pcSet = true;
}
break;
<<<<<<< HEAD
case SYS_INST:
//std::cout << "SYS_INST\n";
temp = reg[rsrc[0]];
if (!c.core->a.is_cpu_mode()) {
//
// GPGPU CSR extension
//
if (immsrc == 0x20) // ThreadID
{
reg[rdest] = t;
D(2, "CSR Reading tid " << hex << immsrc << dec << " and returning " << reg[rdest]);
}
else if (immsrc == 0x21) // WarpID
{
reg[rdest] = c.id;
D(2, "CSR Reading wid " << hex << immsrc << dec << " and returning " << reg[rdest]);
}
else if (immsrc == 0x25)
{
reg[rdest] = c.core->num_instructions;
}
else if (immsrc == 0x26)
{
reg[rdest] = c.core->num_cycles;
}
} else {
switch (func3)
{
case 1:
// printf("Case 1\n");
if (rdest != 0)
{
reg[rdest] = c.csr[immsrc & 0x00000FFF];
}
c.csr[immsrc & 0x00000FFF] = temp;
break;
case 2:
// printf("Case 2\n");
if (rdest != 0)
{
// printf("Reading from CSR: %d = %d\n", (immsrc & 0x00000FFF), c.csr[immsrc & 0x00000FFF]);
reg[rdest] = c.csr[immsrc & 0x00000FFF];
}
// printf("Writing to CSR --> %d = %d\n", immsrc, (temp | c.csr[immsrc & 0x00000FFF]));
c.csr[immsrc & 0x00000FFF] = temp | c.csr[immsrc & 0x00000FFF];
break;
case 3:
// printf("Case 3\n");
if (rdest != 0)
{
reg[rdest] = c.csr[immsrc & 0x00000FFF];
}
c.csr[immsrc & 0x00000FFF] = temp & (~c.csr[immsrc & 0x00000FFF]);
break;
case 5:
// printf("Case 5\n");
if (rdest != 0)
{
reg[rdest] = c.csr[immsrc & 0x00000FFF];
}
c.csr[immsrc & 0x00000FFF] = rsrc[0];
break;
case 6:
// printf("Case 6\n");
if (rdest != 0)
{
reg[rdest] = c.csr[immsrc & 0x00000FFF];
}
c.csr[immsrc & 0x00000FFF] = rsrc[0] | c.csr[immsrc & 0x00000FFF];
break;
case 7:
// printf("Case 7\n");
if (rdest != 0)
{
reg[rdest] = c.csr[immsrc & 0x00000FFF];
}
c.csr[immsrc & 0x00000FFF] = rsrc[0] & (~c.csr[immsrc & 0x00000FFF]);
break;
case 0:
if (immsrc < 2)
{
//std::cout << "INTERRUPT ECALL/EBREAK\n";
nextActiveThreads = 0;
c.spawned = false;
// c.interrupt(0);
}
break;
default:
break;
}
=======
case 4:
// BLT
D(3, "BLT: r" << rsrc[0] << ", r" << rsrc[1] << ", imm=" << (int)immsrc);
@@ -813,7 +714,6 @@ void Instruction::executeOn(Warp &c, trace_inst_t *trace_inst) {
if (!pcSet)
nextPc = (c.pc - 4) + immsrc;
pcSet = true;
>>>>>>> fpga_synthesis
}
break;
case 5:

14
simX/simX.cpp
View File

@@ -59,14 +59,9 @@ HarpToolMode findMode(int argc, char** argv) {
int emu_main(int argc, char **argv) {
string archString("rv32i");
string imgFileName("a.dsfsdout.bin");
<<<<<<< HEAD
bool showHelp, showStats, basicMachine, batch;
bool cpu_mode(false);
=======
bool showHelp(false), showStats(false), basicMachine(true);
int max_warps(NUM_WARPS);
int max_threads(NUM_THREADS);
>>>>>>> fpga_synthesis
/* Read the command line arguments. */
CommandLineArgFlag fh("-h", "--help", "", showHelp);
@@ -74,13 +69,8 @@ int emu_main(int argc, char **argv) {
CommandLineArgSetter<string>fa("-a", "--arch", "", archString);
CommandLineArgFlag fs("-s", "--stats", "", showStats);
CommandLineArgFlag fb("-b", "--basic", "", basicMachine);
<<<<<<< HEAD
CommandLineArgFlag fi("-i", "--batch", "", batch);
CommandLineArgFlag fx("-x", "--cpu", "", cpu_mode);
=======
CommandLineArgSetter<int> fw("-w", "--warps", "", max_warps);
CommandLineArgSetter<int> ft("-t", "--threads", "", max_threads);
>>>>>>> fpga_synthesis
CommandLineArg::readArgs(argc, argv);
@@ -90,11 +80,7 @@ int emu_main(int argc, char **argv) {
}
/* Instantiate a Core, RAM, and console output. */
<<<<<<< HEAD
ArchDef arch(archString, cpu_mode);
=======
ArchDef arch(archString, max_warps, max_threads);
>>>>>>> fpga_synthesis
Decoder *dec;

145
simX/test_riscv.sh
View File

@@ -1,147 +1,3 @@
<<<<<<< HEAD
make
cd obj_dir
echo start > results.txt
echo ./riscv_tests/rv32ui-p-add.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-add.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-addi.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-addi.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-and.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-and.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-andi.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-andi.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-auipc.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-auipc.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-beq.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-beq.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-bge.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-bge.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-bgeu.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-bgeu.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-blt.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-blt.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-bltu.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-bltu.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-bne.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-bne.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-jal.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-jal.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-jalr.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-jalr.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-lb.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-lb.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-lbu.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-lbu.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-lh.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-lh.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-lhu.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-lhu.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-lui.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-lui.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-lw.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-lw.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-or.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-or.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-ori.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-ori.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-sb.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-sb.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-sh.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-sh.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-simple.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-simple.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-sll.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-sll.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-slli.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-slli.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-slt.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-slt.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-slti.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-slti.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-sltiu.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-sltiu.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-sltu.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-sltu.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-sra.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-sra.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-srai.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-srai.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-srl.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-srl.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-srli.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-srli.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-sub.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-sub.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-sw.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-sw.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-xor.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-xor.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-xori.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-xori.hex -s -b >> results.txt
# echo ./riscv_tests/rv32um-p-div.hex >> results.txt
# ./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32um-p-div.hex -s -b >> results.txt
# echo ./riscv_tests/rv32um-p-divu.hex >> results.txt
# ./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32um-p-divu.hex -s -b >> results.txt
# echo ./riscv_tests/rv32um-p-mul.hex >> results.txt
# ./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32um-p-mul.hex -s -b >> results.txt
# echo ./riscv_tests/rv32um-p-mulh.hex >> results.txt
# ./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32um-p-mulh.hex -s -b >> results.txt
# echo ./riscv_tests/rv32um-p-mulhsu.hex >> results.txt
# ./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32um-p-mulhsu.hex -s -b >> results.txt
# echo ./riscv_tests/rv32um-p-mulhu.hex >> results.txt
# ./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32um-p-mulhu.hex -s -b >> results.txt
# echo ./riscv_tests/rv32um-p-rem.hex >> results.txt
# ./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32um-p-rem.hex -s -b >> results.txt
# echo ./riscv_tests/rv32um-p-remu.hex >> results.txt
# ./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32um-p-remu.hex -s -b >> results.txt
=======
#!/bin/bash
make
@@ -285,4 +141,3 @@ echo ./../benchmarks/riscv_tests/rv32ui-p-xori.hex >> results.txt
# echo ./../benchmarks/riscv_tests/rv32um-p-remu.hex >> results.txt
# ./Vcache_simX -E -a rv32i --core ../benchmarks/riscv_tests/rv32um-p-remu.hex -s -b >> results.txt
>>>>>>> fpga_synthesis

17
simX/test_runtime.sh
View File

@@ -1,11 +1,3 @@
<<<<<<< HEAD
make
make -C ../runtime/mains/dev
make -C ../runtime/mains/hello
make -C ../runtime/mains/nativevecadd
make -C ../runtime/mains/simple
make -C ../runtime/mains/vecadd
=======
#!/bin/bash
make
@@ -14,23 +6,14 @@ make -C ../runtime/tests/hello
make -C ../runtime/tests/nativevecadd
make -C ../runtime/tests/simple
make -C ../runtime/tests/vecadd
>>>>>>> fpga_synthesis
cd obj_dir
echo start > results.txt
printf "Fasten your seatbelts ladies and gentelmen!!\n\n\n\n"
<<<<<<< HEAD
#./Vcache_simX -E -a rv32i --core ../../runtime/mains/dev/vx_dev_main.hex -s -b 1> emulator.debug
#./Vcache_simX -E -a rv32i --core ../../runtime/mains/hello/hello.hex -s -b 1> emulator.debug
./Vcache_simX -E -a rv32i --core ../../runtime/mains/nativevecadd/vx_pocl_main.hex -s -b 1> emulator.debug
./Vcache_simX -E -a rv32i --core ../../runtime/mains/simple/vx_simple_main.hex -s -b 1> emulator.debug
./Vcache_simX -E -a rv32i --core ../../runtime/mains/vecadd/vx_pocl_main.hex -s -b 1> emulator.debug
=======
#./Vcache_simX -E -a rv32i --core ../runtime/tests/dev/vx_dev_main.hex -s -b 1> emulator.debug
#./Vcache_simX -E -a rv32i --core ../runtime/tests/hello/hello.hex -s -b 1> emulator.debug
./Vcache_simX -E -a rv32i --core ../runtime/tests/nativevecadd/vx_pocl_main.hex -s -b 1> emulator.debug
./Vcache_simX -E -a rv32i --core ../runtime/tests/simple/vx_simple_main.hex -s -b 1> emulator.debug
./Vcache_simX -E -a rv32i --core ../runtime/tests/vecadd/vx_pocl_main.hex -s -b 1> emulator.debug
>>>>>>> fpga_synthesis