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lkg build with pipeline + FPU fixes

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This commit is contained in:
Blaise Tine
2020-07-31 09:29:44 -04:00
parent 0d82a8aa4f
commit c9755a0c48
33 changed files with 408 additions and 294 deletions
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7
hw/rtl/VX_writeback.v
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@@ -24,9 +24,10 @@ module VX_writeback #(
reg [`NUM_THREADS-1:0] wb_thread_mask [`ISSUEQ_SIZE-1:0];
reg [31:0] wb_curr_PC [`ISSUEQ_SIZE-1:0];
reg [`NR_BITS-1:0] wb_rd [`ISSUEQ_SIZE-1:0];
reg [`ISSUEQ_SIZE-1:0] wb_pending, wb_pending_n;
reg [`ISTAG_BITS-1:0] wb_index;
reg [`ISSUEQ_SIZE-1:0] wb_pending;
reg [`ISSUEQ_SIZE-1:0] wb_pending_n;
reg [`ISTAG_BITS-1:0] wb_index;
wire [`ISTAG_BITS-1:0] wb_index_n;
reg wb_valid;
@@ -67,6 +68,8 @@ module VX_writeback #(
always @(posedge clk) begin
if (reset) begin
wb_pending <= 0;
wb_index <= 0;
wb_valid <= 0;
end else begin
if (alu_commit_if.valid) begin
wb_data [alu_commit_if.issue_tag] <= alu_commit_if.data;