profiling timing optimization

minor update minor update minor update
2023-12-13 18:04:12 -08:00
parent f5f9e3dfdb
commit c6845a4c8d
11 changed files with 64 additions and 56 deletions
--- a/hw/rtl/core/VX_wctl_unit.sv
+++ b/hw/rtl/core/VX_wctl_unit.sv
@@ -49,7 +49,7 @@ module VX_wctl_unit import VX_gpu_pkg::*; #(
    wire is_join   = (execute_if.data.op_type == `INST_SFU_JOIN);
    wire is_bar    = (execute_if.data.op_type == `INST_SFU_BAR);

-    wire [LANE_BITS-1:0] tid;
+    wire [`UP(LANE_BITS)-1:0] tid;
    if (LANE_BITS != 0) begin
        assign tid = execute_if.data.tid[0 +: LANE_BITS];
    end else begin