fixed SCOPE interface
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@@ -4,7 +4,7 @@ module VX_execute #(
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parameter CORE_ID = 0
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) (
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`SCOPE_SIGNALS_LSU_IO
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`SCOPE_SIGNALS_BE_IO
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`SCOPE_SIGNALS_EX_IO
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input wire clk,
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input wire reset,
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@@ -126,24 +126,16 @@ module VX_execute #(
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&& (`BR_OP(alu_req_if.op_type) == `BR_EBREAK
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|| `BR_OP(alu_req_if.op_type) == `BR_ECALL);
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`SCOPE_ASSIGN (scope_decode_valid, decode_if.valid);
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`SCOPE_ASSIGN (scope_decode_wid, decode_if.wid);
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`SCOPE_ASSIGN (scope_decode_curr_PC, decode_if.curr_PC);
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`SCOPE_ASSIGN (scope_decode_is_jal, decode_if.is_jal);
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`SCOPE_ASSIGN (scope_decode_rs1, decode_if.rs1);
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`SCOPE_ASSIGN (scope_decode_rs2, decode_if.rs2);
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`SCOPE_ASSIGN (scope_execute_valid, alu_req_if.valid);
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`SCOPE_ASSIGN (scope_execute_wid, alu_req_if.wid);
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`SCOPE_ASSIGN (scope_execute_curr_PC, alu_req_if.curr_PC);
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`SCOPE_ASSIGN (scope_execute_rd, alu_req_if.rd);
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`SCOPE_ASSIGN (scope_execute_a, alu_req_if.rs1_data);
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`SCOPE_ASSIGN (scope_execute_b, alu_req_if.rs2_data);
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`SCOPE_ASSIGN (scope_alu_req_valid, alu_req_if.valid);
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`SCOPE_ASSIGN (scope_alu_req_wid, alu_req_if.wid);
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`SCOPE_ASSIGN (scope_alu_req_PC, alu_req_if.curr_PC);
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`SCOPE_ASSIGN (scope_alu_req_rd, alu_req_if.rd);
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`SCOPE_ASSIGN (scope_alu_req_a, alu_req_if.rs1_data);
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`SCOPE_ASSIGN (scope_alu_req_b, alu_req_if.rs2_data);
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`SCOPE_ASSIGN (scope_writeback_valid, writeback_if.valid);
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`SCOPE_ASSIGN (scope_writeback_wid, writeback_if.wid);
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`SCOPE_ASSIGN (scope_writeback_curr_PC, writeback_if.curr_PC);
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`SCOPE_ASSIGN (scope_writeback_wb, writeback_if.wb);
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`SCOPE_ASSIGN (scope_writeback_PC, writeback_if.curr_PC);
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`SCOPE_ASSIGN (scope_writeback_rd, writeback_if.rd);
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`SCOPE_ASSIGN (scope_writeback_data, writeback_if.data);
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