fixed SCOPE interface
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@@ -32,6 +32,12 @@ constexpr int ilog2(int n) {
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static constexpr int NW_BITS = ilog2(NUM_WARPS);
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#ifdef EXT_F_ENABLE
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static constexpr int NR_BITS = ilog2(64);
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#else
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static constexpr int NR_BITS = ilog2(32);
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#endif
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static const scope_signal_t scope_signals[] = {
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{ 32, "dram_req_addr" },
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@@ -47,39 +53,32 @@ static const scope_signal_t scope_signals[] = {
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{ 16, "snp_req_tag" },
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{ 16, "snp_rsp_tag" },
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{ NW_BITS, "icache_req_warp_num" },
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{ NW_BITS, "icache_req_wid" },
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{ 32, "icache_req_addr" },
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{ NW_BITS, "icache_req_tag" },
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{ 32, "icache_rsp_data" },
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{ NW_BITS, "icache_rsp_tag" },
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{ NW_BITS, "dcache_req_warp_num" },
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{ 32, "dcache_req_curr_PC" },
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{ 64, "dcache_req_addr" },
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{ NW_BITS, "dcache_req_wid" },
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{ 32, "dcache_req_PC" },
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{ NUM_THREADS * 32, "dcache_req_addr" },
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{ 1, "dcache_req_rw" },
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{ 8, "dcache_req_byteen" },
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{ 64, "dcache_req_data" },
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{ NUM_THREADS * 4, "dcache_req_byteen" },
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{ NUM_THREADS * 32, "dcache_req_data" },
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{ NW_BITS, "dcache_req_tag" },
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{ 64, "dcache_rsp_data" },
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{ NUM_THREADS * 32, "dcache_rsp_data" },
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{ NW_BITS, "dcache_rsp_tag" },
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{ NW_BITS, "decode_warp_num" },
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{ 32, "decode_curr_PC" },
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{ 1, "decode_is_jal" },
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{ 5, "decode_rs1" },
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{ 5, "decode_rs2" },
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{ NW_BITS, "alu_req_wid" },
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{ 32, "alu_req_PC" },
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{ NR_BITS, "alu_req_rd" },
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{ NUM_THREADS * 32, "alu_req_a" },
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{ NUM_THREADS * 32, "alu_req_b" },
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{ NW_BITS, "execute_warp_num" },
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{ 32, "execute_curr_PC" },
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{ 5, "execute_rd" },
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{ 64, "execute_a" },
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{ 64, "execute_b" },
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{ NW_BITS, "writeback_warp_num" },
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{ 32, "writeback_curr_PC" },
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{ 2, "writeback_wb" },
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{ 5, "writeback_rd" },
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{ 64, "writeback_data" },
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{ NW_BITS, "writeback_wid" },
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{ 32, "writeback_PC" },
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{ NR_BITS, "writeback_rd" },
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{ NUM_THREADS * 32, "writeback_data" },
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{ 32, "bank_addr_st0" },
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{ 32, "bank_addr_st1" },
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@@ -112,13 +111,9 @@ static const scope_signal_t scope_signals[] = {
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{ 1, "dcache_rsp_ready" },
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{ NUM_THREADS, "decode_valid" },
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{ NUM_THREADS, "execute_valid" },
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{ NUM_THREADS, "writeback_valid" },
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{ NUM_THREADS, "alu_req_valid" },
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{ NUM_THREADS, "writeback_valid" },
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{ 1, "schedule_delay" },
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{ 1, "mem_delay" },
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{ 1, "exec_delay" },
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{ 1, "gpr_delay" },
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{ 1, "busy" },
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{ 1, "bank_valid_st0" },
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@@ -62,8 +62,8 @@ ifdef AFU
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TOP = vortex_afu_sim
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VL_FLAGS += -DNOPAE
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CFLAGS += -DNOPAE
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#VL_FLAGS += -DSCOPE
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#CFLAGS += -DSCOPE
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VL_FLAGS += -DSCOPE
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CFLAGS += -DSCOPE
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RTL_INCLUDE += -I../../hw/opae -I../../hw/opae/ccip
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endif
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