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replace procedural continuous assignments and force MLAB inference for generic_queue_ll

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wgulian3
2020-03-10 17:46:48 -04:00
parent a931b588c2
commit c5fe43724e
3 changed files with 5 additions and 4 deletions
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4
rtl/VX_cache/VX_cache_req_queue.v
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@@ -166,9 +166,9 @@ module VX_cache_req_queue
always @(*) begin always @(*) begin
assign updated_valids = qual_valids; updated_valids = qual_valids;
if (qual_has_request) begin if (qual_has_request) begin
assign updated_valids[qual_request_index] = 0; updated_valids[qual_request_index] = 0;
end end
end end

2
rtl/VX_cache/VX_snp_fwd_arb.v
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@@ -30,7 +30,7 @@ module VX_snp_fwd_arb
assign snp_fwd_addr = per_bank_snp_fwd_addr[fsq_bank]; assign snp_fwd_addr = per_bank_snp_fwd_addr[fsq_bank];
always @(*) begin always @(*) begin
assign per_bank_snp_fwd_pop = 0; per_bank_snp_fwd_pop = 0;
if (fsq_valid) begin if (fsq_valid) begin
per_bank_snp_fwd_pop[fsq_bank] = 1; per_bank_snp_fwd_pop[fsq_bank] = 1;
end end

3
rtl/VX_generic_queue_ll.v
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@@ -24,7 +24,8 @@ module VX_generic_queue_ll
assign full = 0; assign full = 0;
end else begin end else begin
reg[DATAW-1:0] data[SIZE-1:0], curr_r, head_r; (* syn_ramstyle = "mlab" *) reg[DATAW-1:0] data[SIZE-1:0];
reg[DATAW-1:0] curr_r, head_r;
reg[$clog2(SIZE+1)-1:0] size_r; reg[$clog2(SIZE+1)-1:0] size_r;
reg[$clog2(SIZE)-1:0] wr_ctr_r; reg[$clog2(SIZE)-1:0] wr_ctr_r;
reg[$clog2(SIZE)-1:0] rd_ptr_r, rd_next_ptr_r; reg[$clog2(SIZE)-1:0] rd_ptr_r, rd_next_ptr_r;