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interfaces refactoring

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This commit is contained in:
Blaise Tine
2020-07-02 19:31:55 -07:00
parent ba43e2d33a
commit c5a64a0eed
29 changed files with 295 additions and 297 deletions
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130
hw/rtl/VX_core.v
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@@ -97,18 +97,18 @@ module VX_core #(
.DRAM_TAG_WIDTH(`DDRAM_TAG_WIDTH)
) dcache_dram_rsp_if();
assign D_dram_req_valid = dcache_dram_req_if.dram_req_valid;
assign D_dram_req_rw = dcache_dram_req_if.dram_req_rw;
assign D_dram_req_byteen= dcache_dram_req_if.dram_req_byteen;
assign D_dram_req_addr = dcache_dram_req_if.dram_req_addr;
assign D_dram_req_data = dcache_dram_req_if.dram_req_data;
assign D_dram_req_tag = dcache_dram_req_if.dram_req_tag;
assign dcache_dram_req_if.dram_req_ready = D_dram_req_ready;
assign D_dram_req_valid = dcache_dram_req_if.valid;
assign D_dram_req_rw = dcache_dram_req_if.rw;
assign D_dram_req_byteen= dcache_dram_req_if.byteen;
assign D_dram_req_addr = dcache_dram_req_if.addr;
assign D_dram_req_data = dcache_dram_req_if.data;
assign D_dram_req_tag = dcache_dram_req_if.tag;
assign dcache_dram_req_if.ready = D_dram_req_ready;
assign dcache_dram_rsp_if.dram_rsp_valid = D_dram_rsp_valid;
assign dcache_dram_rsp_if.dram_rsp_data = D_dram_rsp_data;
assign dcache_dram_rsp_if.dram_rsp_tag = D_dram_rsp_tag;
assign D_dram_rsp_ready = dcache_dram_rsp_if.dram_rsp_ready;
assign dcache_dram_rsp_if.valid = D_dram_rsp_valid;
assign dcache_dram_rsp_if.data = D_dram_rsp_data;
assign dcache_dram_rsp_if.tag = D_dram_rsp_tag;
assign D_dram_rsp_ready = dcache_dram_rsp_if.ready;
VX_cache_core_req_if #(
.NUM_REQUESTS(`DNUM_REQUESTS),
@@ -124,18 +124,18 @@ module VX_core #(
.CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS)
) core_dcache_rsp_if(), arb_dcache_rsp_if(), arb_io_rsp_if();
assign io_req_valid = arb_io_req_if.core_req_valid[0];
assign io_req_rw = arb_io_req_if.core_req_rw[0];
assign io_req_byteen = arb_io_req_if.core_req_byteen[0];
assign io_req_addr = arb_io_req_if.core_req_addr[0];
assign io_req_data = arb_io_req_if.core_req_data[0];
assign io_req_tag = arb_io_req_if.core_req_tag[0];
assign arb_io_req_if.core_req_ready = io_req_ready;
assign io_req_valid = arb_io_req_if.valid[0];
assign io_req_rw = arb_io_req_if.rw[0];
assign io_req_byteen = arb_io_req_if.byteen[0];
assign io_req_addr = arb_io_req_if.addr[0];
assign io_req_data = arb_io_req_if.data[0];
assign io_req_tag = arb_io_req_if.tag[0];
assign arb_io_req_if.ready = io_req_ready;
assign arb_io_rsp_if.core_rsp_valid = {{(`NUM_THREADS-1){1'b0}}, io_rsp_valid};
assign arb_io_rsp_if.core_rsp_data[0] = io_rsp_data;
assign arb_io_rsp_if.core_rsp_tag = io_rsp_tag;
assign io_rsp_ready = arb_io_rsp_if.core_rsp_ready;
assign arb_io_rsp_if.valid = {{(`NUM_THREADS-1){1'b0}}, io_rsp_valid};
assign arb_io_rsp_if.data[0] = io_rsp_data;
assign arb_io_rsp_if.tag = io_rsp_tag;
assign io_rsp_ready = arb_io_rsp_if.ready;
// Icache interfaces
@@ -150,18 +150,18 @@ module VX_core #(
.DRAM_TAG_WIDTH(`IDRAM_TAG_WIDTH)
) icache_dram_rsp_if();
assign I_dram_req_valid = icache_dram_req_if.dram_req_valid;
assign I_dram_req_rw = icache_dram_req_if.dram_req_rw;
assign I_dram_req_byteen= icache_dram_req_if.dram_req_byteen;
assign I_dram_req_addr = icache_dram_req_if.dram_req_addr;
assign I_dram_req_data = icache_dram_req_if.dram_req_data;
assign I_dram_req_tag = icache_dram_req_if.dram_req_tag;
assign icache_dram_req_if.dram_req_ready = I_dram_req_ready;
assign I_dram_req_valid = icache_dram_req_if.valid;
assign I_dram_req_rw = icache_dram_req_if.rw;
assign I_dram_req_byteen= icache_dram_req_if.byteen;
assign I_dram_req_addr = icache_dram_req_if.addr;
assign I_dram_req_data = icache_dram_req_if.data;
assign I_dram_req_tag = icache_dram_req_if.tag;
assign icache_dram_req_if.ready = I_dram_req_ready;
assign icache_dram_rsp_if.dram_rsp_valid = I_dram_rsp_valid;
assign icache_dram_rsp_if.dram_rsp_data = I_dram_rsp_data;
assign icache_dram_rsp_if.dram_rsp_tag = I_dram_rsp_tag;
assign I_dram_rsp_ready = icache_dram_rsp_if.dram_rsp_ready;
assign icache_dram_rsp_if.valid = I_dram_rsp_valid;
assign icache_dram_rsp_if.data = I_dram_rsp_data;
assign icache_dram_rsp_if.tag = I_dram_rsp_tag;
assign I_dram_rsp_ready = icache_dram_rsp_if.ready;
VX_cache_core_req_if #(
.NUM_REQUESTS(`INUM_REQUESTS),
@@ -189,34 +189,34 @@ module VX_core #(
.reset(reset),
// Dcache core request
.dcache_req_valid (core_dcache_req_if.core_req_valid),
.dcache_req_rw (core_dcache_req_if.core_req_rw),
.dcache_req_byteen (core_dcache_req_if.core_req_byteen),
.dcache_req_addr (core_dcache_req_if.core_req_addr),
.dcache_req_data (core_dcache_req_if.core_req_data),
.dcache_req_tag (core_dcache_req_if.core_req_tag),
.dcache_req_ready (core_dcache_req_if.core_req_ready),
.dcache_req_valid (core_dcache_req_if.valid),
.dcache_req_rw (core_dcache_req_if.rw),
.dcache_req_byteen (core_dcache_req_if.byteen),
.dcache_req_addr (core_dcache_req_if.addr),
.dcache_req_data (core_dcache_req_if.data),
.dcache_req_tag (core_dcache_req_if.tag),
.dcache_req_ready (core_dcache_req_if.ready),
// Dcache core reponse
.dcache_rsp_valid (core_dcache_rsp_if.core_rsp_valid),
.dcache_rsp_data (core_dcache_rsp_if.core_rsp_data),
.dcache_rsp_tag (core_dcache_rsp_if.core_rsp_tag),
.dcache_rsp_ready (core_dcache_rsp_if.core_rsp_ready),
.dcache_rsp_valid (core_dcache_rsp_if.valid),
.dcache_rsp_data (core_dcache_rsp_if.data),
.dcache_rsp_tag (core_dcache_rsp_if.tag),
.dcache_rsp_ready (core_dcache_rsp_if.ready),
// Dcache core request
.icache_req_valid (core_icache_req_if.core_req_valid),
.icache_req_rw (core_icache_req_if.core_req_rw),
.icache_req_byteen (core_icache_req_if.core_req_byteen),
.icache_req_addr (core_icache_req_if.core_req_addr),
.icache_req_data (core_icache_req_if.core_req_data),
.icache_req_tag (core_icache_req_if.core_req_tag),
.icache_req_ready (core_icache_req_if.core_req_ready),
.icache_req_valid (core_icache_req_if.valid),
.icache_req_rw (core_icache_req_if.rw),
.icache_req_byteen (core_icache_req_if.byteen),
.icache_req_addr (core_icache_req_if.addr),
.icache_req_data (core_icache_req_if.data),
.icache_req_tag (core_icache_req_if.tag),
.icache_req_ready (core_icache_req_if.ready),
// Dcache core reponse
.icache_rsp_valid (core_icache_rsp_if.core_rsp_valid),
.icache_rsp_data (core_icache_rsp_if.core_rsp_data),
.icache_rsp_tag (core_icache_rsp_if.core_rsp_tag),
.icache_rsp_ready (core_icache_rsp_if.core_rsp_ready),
.icache_rsp_valid (core_icache_rsp_if.valid),
.icache_rsp_data (core_icache_rsp_if.data),
.icache_rsp_tag (core_icache_rsp_if.tag),
.icache_rsp_ready (core_icache_rsp_if.ready),
// CSR I/O request
.csr_io_req_valid (csr_io_req_valid),
@@ -246,15 +246,15 @@ module VX_core #(
.SNP_TAG_WIDTH(`DSNP_TAG_WIDTH)
) dcache_snp_rsp_if();
assign dcache_snp_req_if.snp_req_valid = snp_req_valid;
assign dcache_snp_req_if.snp_req_addr = snp_req_addr;
assign dcache_snp_req_if.snp_req_invalidate = snp_req_invalidate;
assign dcache_snp_req_if.snp_req_tag = snp_req_tag;
assign snp_req_ready = dcache_snp_req_if.snp_req_ready;
assign dcache_snp_req_if.valid = snp_req_valid;
assign dcache_snp_req_if.addr = snp_req_addr;
assign dcache_snp_req_if.invalidate = snp_req_invalidate;
assign dcache_snp_req_if.tag = snp_req_tag;
assign snp_req_ready = dcache_snp_req_if.ready;
assign snp_rsp_valid = dcache_snp_rsp_if.snp_rsp_valid;
assign snp_rsp_tag = dcache_snp_rsp_if.snp_rsp_tag;
assign dcache_snp_rsp_if.snp_rsp_ready = snp_rsp_ready;
assign snp_rsp_valid = dcache_snp_rsp_if.valid;
assign snp_rsp_tag = dcache_snp_rsp_if.tag;
assign dcache_snp_rsp_if.ready = snp_rsp_ready;
VX_mem_unit #(
.CORE_ID(CORE_ID)
@@ -284,8 +284,8 @@ module VX_core #(
);
// select io address
wire is_io_addr = ({core_dcache_req_if.core_req_addr[0], 2'b0} >= `IO_BUS_BASE_ADDR);
wire io_select = (| core_dcache_req_if.core_req_valid) ? is_io_addr : 0;
wire is_io_addr = ({core_dcache_req_if.addr[0], 2'b0} >= `IO_BUS_BASE_ADDR);
wire io_select = (| core_dcache_req_if.valid) ? is_io_addr : 0;
VX_dcache_arb dcache_io_arb (
.req_select (io_select),