modelsim fixes && pipeline optimization

2020-07-28 14:20:23 -07:00
parent 1c9846d10b
commit c2dd0a8b39
38 changed files with 417 additions and 358 deletions
--- a/hw/rtl/libs/VX_cam_buffer.v
+++ b/hw/rtl/libs/VX_cam_buffer.v
@@ -1,4 +1,4 @@
-`include "VX_define.vh"
+`include "VX_platform.vh"

 module VX_cam_buffer #(
    parameter DATAW    = 1,
@@ -43,7 +43,7 @@ module VX_cam_buffer #(
            if (release_slot[i]) begin
                free_slots_n[read_addr[i]] = 1;                
            end
-            assign read_data[i] = entries[read_addr[i]];            
+            read_data[i] = entries[read_addr[i]];            
        end
    end