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modelsim fixes && pipeline optimization

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This commit is contained in:
Blaise Tine
2020-07-28 14:20:23 -07:00
parent 1c9846d10b
commit c2dd0a8b39
38 changed files with 417 additions and 358 deletions
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9
hw/rtl/VX_commit.v
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@@ -65,8 +65,6 @@ module VX_commit #(
assign cmt_to_issue_if.fpu_tag = fpu_commit_if.issue_tag;
assign cmt_to_issue_if.gpu_tag = gpu_commit_if.issue_tag;
assign gpu_commit_if.ready = 1'b1; // doesn't writeback
VX_writeback #(
.CORE_ID(CORE_ID)
) writeback (
@@ -77,9 +75,10 @@ module VX_commit #(
.lsu_commit_if (lsu_commit_if),
.csr_commit_if (csr_commit_if),
.mul_commit_if (mul_commit_if),
.fpu_commit_if (fpu_commit_if),
.cmt_to_issue_if(cmt_to_issue_if),
.fpu_commit_if (fpu_commit_if),
.gpu_commit_if (gpu_commit_if),
.cmt_to_issue_if(cmt_to_issue_if),
.writeback_if (writeback_if)
);