SimX timing simulation

sim/simX/core.h

@@ -4,10 +4,11 @@
 #include <vector>
 #include <list>
 #include <stack>
+#include <queue>
 #include <unordered_map>
 #include <memory>
 #include <set>
-
+#include <simobject.h>
 #include "debug.h"
 #include "types.h"
 #include "archdef.h"
@@ -15,20 +16,21 @@
 #include "mem.h"
 #include "warp.h"
 #include "pipeline.h"
+#include "cache.h"
+#include "ibuffer.h"
+#include "scoreboard.h"
+#include "exeunit.h"
 
 namespace vortex {
 
-class Core {
+class Core : public SimObject<Core> {
 public:
-  Core(const ArchDef &arch, Decoder &decoder, MemoryUnit &mem, Word id);
-
+  Core(const SimContext& ctx, const ArchDef &arch, Decoder &decoder, MemoryUnit &mem, Word id);
   ~Core();
 
-  void clear();
-
   bool running() const;
 
-  void step();
+  void step(uint64_t cycle);
 
   void printStats() const;
 
@@ -40,7 +42,7 @@ public:
     return *warps_.at(i);
   }
 
-  Decoder& decoder() {
+  const Decoder& decoder() {
     return decoder_;
   }
 
@@ -48,16 +50,12 @@ public:
     return arch_;
   }
 
-  unsigned long num_insts() const {
-    return insts_;
-  }
-
-  unsigned long num_steps() const {
-    return steps_;
+  unsigned long stats_insts() const {
+    return stats_insts_;
   } 
 
   Word getIRegValue(int reg) const {
-    return warps_[0]->getIRegValue(reg);
+    return warps_.at(0)->getIRegValue(reg);
   }
 
   Word get_csr(Addr addr, int tid, int wid);
@@ -73,50 +71,66 @@ public:
   void dcache_write(Addr, Word, Size);
 
   void trigger_ebreak();
+
   bool check_ebreak() const;
 
-private: 
+private:
 
-  void schedule();
   void fetch();
   void decode();
   void issue();
   void execute();
-  void writeback();
+  void commit();
+
+  void warp_scheduler();
+
+  void icache_handleCacheReponse(const MemRsp& response, uint32_t port_id);
 
   void writeToStdOut(Addr addr, Word data);
-  
-  std::vector<RegMask> in_use_iregs_;
-  std::vector<RegMask> in_use_fregs_;
-  RegMask in_use_vregs_;
-  WarpMask stalled_warps_;
-  std::vector<std::shared_ptr<Warp>> warps_;  
-  std::vector<WarpMask> barriers_;  
-  std::vector<Word> csrs_;
-  std::vector<Byte> fcsrs_;
-  std::unordered_map<int, std::stringstream> print_bufs_;
 
   Word id_;
-  const ArchDef &arch_;
-  Decoder &decoder_;
-  MemoryUnit &mem_;
+  const ArchDef& arch_;
+  const Decoder& decoder_;
+  MemoryUnit& mem_;
 #ifdef SM_ENABLE
   RAM shared_mem_;
 #endif 
 
+  std::vector<std::shared_ptr<Warp>> warps_;  
+  std::vector<WarpMask> barriers_;  
+  std::vector<Word> csrs_;
+  std::vector<Byte> fcsrs_;
+  std::vector<IBuffer> ibuffers_;
+  Scoreboard scoreboard_;
+  std::vector<ExeUnit::Ptr> exe_units_;
+  Cache::Ptr icache_;
+  Cache::Ptr dcache_;
+  Switch<MemReq, MemRsp>::Ptr l1_mem_switch_;
+  SlavePort<MemRsp> icache_rsp_port_;
+  std::vector<SlavePort<MemRsp>> dcache_rsp_port_;
+
+  PipelineStage fetch_stage_;
+  PipelineStage decode_stage_;
+  PipelineStage issue_stage_;
+  PipelineStage execute_stage_;
+  PipelineStage commit_stage_;  
+  
+  HashTable<pipeline_state_t> pending_icache_;
+  WarpMask stalled_warps_;  
+  uint32_t last_schedule_wid_;
+  uint32_t pending_instrs_;
   bool ebreak_;
 
-  Pipeline inst_in_schedule_;
-  Pipeline inst_in_fetch_;
-  Pipeline inst_in_decode_;
-  Pipeline inst_in_issue_;
-  Pipeline inst_in_execute_;
-  Pipeline inst_in_writeback_;
+  std::unordered_map<int, std::stringstream> print_bufs_;
+  uint64_t stats_insts_;
+  uint64_t stats_loads_;
+  uint64_t stats_stores_;
 
-  uint64_t steps_;
-  uint64_t insts_;
-  uint64_t loads_;
-  uint64_t stores_; 
+  friend class LsuUnit;
+
+public:
+  SlavePort<MemRsp>  MemRspPort;
+  MasterPort<MemReq> MemReqPort;
 };
 
 } // namespace vortex