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tex sampler unit test pass - pt sampling, rgba8

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This commit is contained in:
Krishna Yalamarthy
2021-03-27 19:35:14 -04:00
parent 02e093d407
commit c1e25135fd
4 changed files with 382 additions and 195 deletions
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13
hw/rtl/tex_unit/VX_tex_sampler.v
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@@ -54,18 +54,11 @@ module VX_tex_sampler #(
.formatted_texel(formatted_data) .formatted_texel(formatted_data)
); );
//blendU/blendV calculation
wire [`BLEND_FRAC_64-1:0] blendU;
wire [`BLEND_FRAC_64-1:0] blendV;
assign blendU = req_u[i][`BLEND_FRAC_64-1:0];
assign blendV = req_v[i][`BLEND_FRAC_64-1:0];
VX_tex_bilerp #( VX_tex_bilerp #(
.CORE_ID (CORE_ID) .CORE_ID (CORE_ID)
) tex_bilerp ( ) tex_bilerp (
.blendU(blendU), //blendU .blendU(req_u[i][`BLEND_FRAC_64-1:0]), //blendU
.blendV(blendV), //blendV .blendV(req_v[i][`BLEND_FRAC_64-1:0]), //blendV
.color_enable(color_enable), .color_enable(color_enable),
.texels(formatted_data), .texels(formatted_data),
@@ -76,7 +69,7 @@ module VX_tex_sampler #(
end end
for (genvar i = 0;i<`NUM_THREADS ;i++ ) begin for (genvar i = 0;i<`NUM_THREADS ;i++ ) begin
assign req_data[i] = (req_filter == `TEX_FILTER_BITS'h0) ? req_texels[i][0] : req_data_bilerp[i]; assign req_data[i] = (req_filter == `TEX_FILTER_BITS'(0)) ? req_texels[i][0] : req_data_bilerp[i];
end end
assign stall_out = ~rsp_ready; assign stall_out = ~rsp_ready;

314
hw/unit_tests/tex_unit/tex_sampler/main.cpp
View File

@@ -1,12 +1,52 @@
#include "vl_simulator.h" #include "vl_simulator.h"
#include "VVX_tex_sampler.h" #include "VVX_tex_sampler.h"
#include <iostream> #include <iostream>
#include <map>
#define MAX_TICKS 20 #define MAX_TICKS 20
#define MAX_UNIT_CYCLES 5
#define NUM_THREADS #define NUM_THREADS
// // outputs
// bool req_ready;
// bool rsp_valid;
// unsigned int rsp_wid;
// unsigned int rsp_tmask;
// unsigned int rsp_PC;
// unsigned int rsp_rd;
// bool rsp_wb;
// unsigned int rsp_data[NUM_THREADS];
// if (input != input_map.end()){
// sim->req_valid = input->req_valid;
// sim->req_wid = input->req_wid;
// sim->req_tmask = input->req_tmask;
// sim->req_PC = input->req_PC;
// sim->req_rd = input->req_rd;
// sim->req_wb = input->req_wb;
// sim->req_filter = input->req_filter;
// sim->req_format = input->req_format;
// // sim->req_u = input->req_u[NUM_THREADS];
// // sim->req_v = input->req_v[NUM_THREADS];
// vl_setw(sim->req_texels, input->req_texels)
// // sim->req_texels = input->req_texels[NUM_THREADS][4];
// sim->rsp_ready = input->rsp_ready;
// } else{
// std::cout << "Warning! No Input on Cycle " << cycle << std::endl;
// }
// if(output != output_map.end()){
// CHECK(sim->req_ready == output->req_ready);
// CHECK(sim->rsp_valid == output->rsp_valid);
// CHECK(sim->rsp_wid == output->rsp_wid);
// CHECK(sim->rsp_tmask == output->rsp_tmask);
// CHECK(sim->rsp_PC == output->rsp_PC);
// CHECK(sim->rsp_rd == output->rsp_rd);
// CHECK(sim->rsp_wb == output->rsp_wb);
// CHECK(vl_cmpw(sim->rsp_data, output->rsp_data));
// }
#define CHECK(x) \ #define CHECK(x) \
do { \ do { \
if (x) \ if (x) \
@@ -17,199 +57,103 @@
uint64_t ticks = 0; uint64_t ticks = 0;
// using Device = VVX_tex_sampler;
template <typename T>
class testbench
{
private:
vl_simulator<T> sim;
std::map<int, struct Input> input_map;
std::map<int, struct Output> output_map;
public:
struct UnitTest {
bool use_reset;
unsigned int num_cycles;
bool use_cmodel;
struct Output outputs[MAX_UNIT_CYCLES];
struct Input inputs[MAX_UNIT_CYCLES];
unsigned int num_output_check;
unsigned int check_output_cycle[MAX_UNIT_CYCLES];
}
struct Input {
bool req_valid;
unsigned int req_wid;
unsigned int req_tmask;
unsigned int req_PC;
unsigned int req_rd;
unsigned int req_wb;
unsigned int req_filter;
unsigned int req_format;
unsigned int req_u[NUM_THREADS];
unsigned int req_v[NUM_THREADS];
unsigned int req_texels[NUM_THREADS][4];
bool rsp_ready;
}
struct Output {
int output_cycle;
// outputs
bool req_ready;
bool rsp_valid;
unsigned int rsp_wid;
unsigned int rsp_tmask;
unsigned int rsp_PC;
unsigned int rsp_rd;
bool rsp_wb;
unsigned int rsp_data[NUM_THREADS];
}
testbench(/* args */){
}
~testbench(){
}
void unittest_Cmodel(struct UnitTest * test){
int cycles = test->num_cycles;
int num_outputs = test->num_output_check;
// struct Input* inputs = new (struct Input)[cycles];
struct Output* outputs = new (struct Output)[num_outputs];
// implement c model and assign outputs to struct
if (test->inputs[0]->req_filter == 0){
for (int i = 0; i < NUM_THREADS; i++)
outputs[0]->rsp_data[0] = test->inputs->req_texels[i][0];
} else {
// for (int i = 0; i < NUM_THREADS; i++){
// uint32_t low[4], high[4];
// for (int j = 0; j < 4; j++){
// low[j] = test->inputs->req_texels[i][j] & 0x00ff00ff;
// high[j] = (test->inputs->req_texels[i][j] >> 8) & 0x00ff00ff;
// }
// }
}
outputs[0]->output_cycle = 1;
test->num_cycles = 1;
test->outputs = &outputs;
}
void generate_test_vectors(struct UnitTest * tests, int num_tests, bool is_pipe){
// for all unit tests create output test vectors (w w/o c-model)
int prev_test_cycle = 0;
for (int i = 0; i < num_tests; i++)
{
int op_counter = 0;
int ip_counter = 0;
int test_cycle = 0;
int last_ip_cycle = 0;
struct UnitTest curr_test = tests[i];
if (curr_test->use_cmodel){
unittest_Cmodel(&curr_test);
}
for (int j = 0; j < curr_test->num_cycles; j++)
{
if (curr_test->inputs[ip_counter]->input_cycle == test_cycle){
input_map.insert(std::make_pair(prev_test_cycle + test_cycle, curr_test->inputs[j]));
last_ip_cycle = prev_test_cycle + test_cycle;
ip_counter++;
}
if (curr_test->outputs[op_counter]->output_cycle == test_cycle){
output_map.insert(std::make_pair(prev_test_cycle + test_cycle, curr_test->outputs[op_counter]));
op_counter++;
}
test_cycle++;
}
if(!is_pipe){
prev_test_cycle += (test_cycle - 1);
}
else{
prev_test_cycle = last_ip_cycle + 1;
}
}
}
void run(){
ticks = sim.reset(0);
int cycle = 0;
while (ticks < MAX_TICKS) {
auto input = input_map.find(cycle);
auto output = output_map.find(cycle);
if (input != input_map.end()){
sim->req_valid = input->req_valid;
sim->req_wid = input->req_wid;
sim->req_tmask = input->req_tmask;
sim->req_PC = input->req_PC;
sim->req_rd = input->req_rd;
sim->req_wb = input->req_wb;
sim->req_filter = input->req_filter;
sim->req_format = input->req_format;
// sim->req_u = input->req_u[NUM_THREADS];
// sim->req_v = input->req_v[NUM_THREADS];
vl_setw(sim->req_texels, input->req_texels)
// sim->req_texels = input->req_texels[NUM_THREADS][4];
sim->rsp_ready = input->rsp_ready;
} else{
std::cout << "Warning! No Input on Cycle " << cycle << std::endl;
}
if(output != output_map.end()){
CHECK(sim->req_ready == output->req_ready);
CHECK(sim->rsp_valid == output->rsp_valid);
CHECK(sim->rsp_wid == output->rsp_wid);
CHECK(sim->rsp_tmask == output->rsp_tmask);
CHECK(sim->rsp_PC == output->rsp_PC);
CHECK(sim->rsp_rd == output->rsp_rd);
CHECK(sim->rsp_wb == output->rsp_wb);
CHECK(vl_cmpw(sim->rsp_data, output->rsp_data));
}
cycle++;
ticks = sim.step(ticks,2);
}
}
std::cout << "PASSED!" << std::endl;
std::cout << "Simulation time: " << std::dec << ticks/2 << " cycles" << std::endl;
};
double sc_time_stamp() { double sc_time_stamp() {
return ticks; return ticks;
} }
using Device = VVX_tex_sampler;
int main(int argc, char **argv) { int main(int argc, char **argv) {
// Initialize Verilators variables // Initialize Verilators variables
Verilated::commandArgs(argc, argv); Verilated::commandArgs(argc, argv);
testbench<VVX_tex_sampler> sampler_testbench; vl_simulator<Device> sim;
sampler_testbench.generate_test_vectors(tests, 1, 0); // run test
sampler_test_bench.run(); ticks = sim.reset(0);
while (ticks < MAX_TICKS) {
switch (ticks) {
case 0:
std::cout << "cycle 1" << std::endl;
// input values
sim->req_valid = 1;
sim->req_wid = 3;
sim->req_tmask = 11;
sim->req_PC = 0x0505;
sim->req_wb = 1;
sim->req_filter = 0;
sim->req_format = 3;
sim->rsp_ready = 1;
break;
case 2:
std::cout << "cycle 2" << std::endl;
sim->req_valid = 1;
sim->req_wid = 0;
sim->req_tmask = 15;
sim->req_PC = 0x0515;
sim->req_wb = 1;
sim->req_filter = 0;
sim->req_format = 3;
vl_setw(sim->req_texels, 0xffff, 0xfffa, 0xfffb, 0xfffc,
0xfffd, 0xafff, 0xbfff, 0xcfff,
0xdfff, 0xabcd, 0xdfdd, 0xeabf,
0xaaaa, 0xbbbb, 0xcccc, 0xdddd);
sim->rsp_ready = 1;
break;
case 4:
//bilerp input r8b8g8a8
std::cout << "cycle 3: point sampling check" << std::endl;
sim->req_valid = 1;
sim->rsp_ready = 1;
sim->req_wid = 0;
sim->req_tmask = 15;
sim->req_PC = 0x0519;
// sim->req_rd = req_rd;
sim->req_wb = 1;
sim->req_filter = 1;
sim->req_format = 3;
/*
1u ------- 0u 1v ------- 1v tex0 ------- tex1
| | | | | |
| | | | | |
| | | | | |
1u ------- 0u 0v ------- 0v tex2 ------- tex3
*/
vl_packsetw(sim->req_u, 20, 0x0080, 0x0000, 0x0080, 0x0040); // 1/2, 0, 1/2, 1/4
vl_packsetw(sim->req_v, 20, 0x0000, 0x0080, 0x0080, 0x0040); // 0, 1/2, 1/2, 1/4
// vl_setw(sim->req_texels, 0xffff, 0xfffa, 0xfffb, 0xfffc, 0xfffd, 0xafff, 0xbfff, 0xcfff, 0xdfff, 0xabcd, 0xdfdd, 0xeabf, 0xaaaa, 0xbbbb, 0xcccc, 0xdddd);
// vl_setw(sim->req_texels, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000);
vl_setw(sim->req_texels, 0xffffffff, 0x00000000, 0xffffffff, 0x00000000,
0x00000000, 0xffffffff, 0x00000000, 0x00000000,
0xffffffff, 0x00000000, 0xffffffff, 0x00000000,
0xffffffff, 0x00000000, 0xffffffff, 0x00000000);
// point sampling output check
CHECK(!vl_cmpw(sim->rsp_data, 0xffff, 0xfffd, 0xdfff, 0xaaaa));
break;
case 6:
sim->req_valid = 1;
sim->rsp_ready = 1;
// bilerp sampling output check
std::cout << "cycle 4: bilerp r8g8b8a8 check" << std::endl;
CHECK(!vl_cmpw(sim->rsp_data, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x3f3f3f3f));
}
// advance clock
ticks = sim.step(ticks, 2);
}
std::cout << "PASSED!" << std::endl;
std::cout << "Simulation time: " << std::dec << ticks/2 << " cycles" << std::endl;
return 0; return 0;
} }

215
hw/unit_tests/tex_unit/tex_sampler/main.cpp.copy Normal file
View File

@@ -0,0 +1,215 @@
#include "vl_simulator.h"
#include "VVX_tex_sampler.h"
#include <iostream>
#include <map>
#define MAX_TICKS 20
#define MAX_UNIT_CYCLES 5
#define NUM_THREADS
#define CHECK(x) \
do { \
if (x) \
break; \
std::cout << "FAILED: " << #x << std::endl; \
std::abort(); \
} while (false)
uint64_t ticks = 0;
// using Device = VVX_tex_sampler;
template <typename T>
class testbench
{
private:
vl_simulator<T> sim;
std::map<int, struct Input> input_map;
std::map<int, struct Output> output_map;
public:
struct UnitTest {
bool use_reset;
unsigned int num_cycles;
bool use_cmodel;
struct Output outputs[MAX_UNIT_CYCLES];
struct Input inputs[MAX_UNIT_CYCLES];
unsigned int num_output_check;
unsigned int check_output_cycle[MAX_UNIT_CYCLES];
}
struct Input {
bool req_valid;
unsigned int req_wid;
unsigned int req_tmask;
unsigned int req_PC;
unsigned int req_rd;
unsigned int req_wb;
unsigned int req_filter;
unsigned int req_format;
unsigned int req_u[NUM_THREADS];
unsigned int req_v[NUM_THREADS];
unsigned int req_texels[NUM_THREADS][4];
bool rsp_ready;
}
struct Output {
int output_cycle;
// outputs
bool req_ready;
bool rsp_valid;
unsigned int rsp_wid;
unsigned int rsp_tmask;
unsigned int rsp_PC;
unsigned int rsp_rd;
bool rsp_wb;
unsigned int rsp_data[NUM_THREADS];
}
testbench(/* args */){
}
~testbench(){
}
void unittest_Cmodel(struct UnitTest * test){
int cycles = test->num_cycles;
int num_outputs = test->num_output_check;
// struct Input* inputs = new (struct Input)[cycles];
struct Output* outputs = new (struct Output)[num_outputs];
// implement c model and assign outputs to struct
if (test->inputs[0]->req_filter == 0){
for (int i = 0; i < NUM_THREADS; i++)
outputs[0]->rsp_data[0] = test->inputs->req_texels[i][0];
} else {
// for (int i = 0; i < NUM_THREADS; i++){
// uint32_t low[4], high[4];
// for (int j = 0; j < 4; j++){
// low[j] = test->inputs->req_texels[i][j] & 0x00ff00ff;
// high[j] = (test->inputs->req_texels[i][j] >> 8) & 0x00ff00ff;
// }
// }
}
outputs[0]->output_cycle = 1;
test->num_cycles = 1;
test->outputs = &outputs;
}
void generate_test_vectors(struct UnitTest * tests, int num_tests, bool is_pipe){
// for all unit tests create output test vectors (w w/o c-model)
int prev_test_cycle = 0;
for (int i = 0; i < num_tests; i++)
{
int op_counter = 0;
int ip_counter = 0;
int test_cycle = 0;
int last_ip_cycle = 0;
struct UnitTest curr_test = tests[i];
if (curr_test->use_cmodel){
unittest_Cmodel(&curr_test);
}
for (int j = 0; j < curr_test->num_cycles; j++)
{
if (curr_test->inputs[ip_counter]->input_cycle == test_cycle){
input_map.insert(std::make_pair(prev_test_cycle + test_cycle, curr_test->inputs[j]));
last_ip_cycle = prev_test_cycle + test_cycle;
ip_counter++;
}
if (curr_test->outputs[op_counter]->output_cycle == test_cycle){
output_map.insert(std::make_pair(prev_test_cycle + test_cycle, curr_test->outputs[op_counter]));
op_counter++;
}
test_cycle++;
}
if(!is_pipe){
prev_test_cycle += (test_cycle - 1);
}
else{
prev_test_cycle = last_ip_cycle + 1;
}
}
}
void run(){
ticks = sim.reset(0);
int cycle = 0;
while (ticks < MAX_TICKS) {
auto input = input_map.find(cycle);
auto output = output_map.find(cycle);
if (input != input_map.end()){
sim->req_valid = input->req_valid;
sim->req_wid = input->req_wid;
sim->req_tmask = input->req_tmask;
sim->req_PC = input->req_PC;
sim->req_rd = input->req_rd;
sim->req_wb = input->req_wb;
sim->req_filter = input->req_filter;
sim->req_format = input->req_format;
// sim->req_u = input->req_u[NUM_THREADS];
// sim->req_v = input->req_v[NUM_THREADS];
vl_setw(sim->req_texels, input->req_texels)
// sim->req_texels = input->req_texels[NUM_THREADS][4];
sim->rsp_ready = input->rsp_ready;
} else{
std::cout << "Warning! No Input on Cycle " << cycle << std::endl;
}
if(output != output_map.end()){
CHECK(sim->req_ready == output->req_ready);
CHECK(sim->rsp_valid == output->rsp_valid);
CHECK(sim->rsp_wid == output->rsp_wid);
CHECK(sim->rsp_tmask == output->rsp_tmask);
CHECK(sim->rsp_PC == output->rsp_PC);
CHECK(sim->rsp_rd == output->rsp_rd);
CHECK(sim->rsp_wb == output->rsp_wb);
CHECK(vl_cmpw(sim->rsp_data, output->rsp_data));
}
cycle++;
ticks = sim.step(ticks,2);
}
}
std::cout << "PASSED!" << std::endl;
std::cout << "Simulation time: " << std::dec << ticks/2 << " cycles" << std::endl;
};
double sc_time_stamp() {
return ticks;
}
int main(int argc, char **argv) {
// Initialize Verilators variables
Verilated::commandArgs(argc, argv);
testbench<VVX_tex_sampler> sampler_testbench;
sampler_testbench.generate_test_vectors(tests, 1, 0);
sampler_testbench.run();
return 0;
}

35
hw/unit_tests/tex_unit/tex_sampler/vl_simulator.h
View File

@@ -3,6 +3,7 @@
#include <array> #include <array>
#include <cstdint> #include <cstdint>
#include "verilated.h" #include "verilated.h"
#include <iostream>
#ifdef VM_TRACE #ifdef VM_TRACE
#include <verilated_vcd_c.h> // Trace file format header #include <verilated_vcd_c.h> // Trace file format header
@@ -68,6 +69,40 @@ void vl_setw(uint32_t* sig, Args&&... args) {
} }
} }
template <typename... Args>
void vl_packsetw(uint32_t* sig, int in_width, Args&&... args) {
std::array<uint32_t, sizeof... (Args)> arr{static_cast<uint32_t>(std::forward<Args>(args))...};
std::array<uint32_t, sizeof... (Args)> packed_arr;
int rem = in_width;
size_t j = 0;
for (size_t i = 0; i < (sizeof... (Args)*in_width)/32 + 1; ++i) {
packed_arr[i] = 0;
int bits = 0;
while (bits<32)
{
if (32-bits>rem)
{
packed_arr[i] = ( ( (arr[j] & ( ((1<<rem)-1) << (in_width-rem) ) ) >> in_width-rem) << bits ) | packed_arr[i];
bits += rem;
rem = in_width;
j++;
}
else
{
packed_arr[i] = (arr[j] & ((1<<rem)-1)) << bits | packed_arr[i];
rem -= (32-bits);
bits = 33;
}
}
}
for (size_t i = 0; i < (sizeof... (Args)*in_width)/32 + 1; ++i) {
sig[i] = packed_arr[i];
}
}
template <typename... Args> template <typename... Args>
int vl_cmpw(const uint32_t* sig, Args&&... args) { int vl_cmpw(const uint32_t* sig, Args&&... args) {
std::array<uint32_t, sizeof... (Args)> arr{static_cast<uint32_t>(std::forward<Args>(args))...}; std::array<uint32_t, sizeof... (Args)> arr{static_cast<uint32_t>(std::forward<Args>(args))...};