Vortex 2.0 changes:
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
This commit is contained in:
Blaise Tine
363
sim/simx/types.h
363
sim/simx/types.h
@@ -1,3 +1,16 @@
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// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#include <stdint.h>
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@@ -5,31 +18,42 @@
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#include <queue>
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#include <unordered_map>
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#include <util.h>
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#include <stringutil.h>
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#include <VX_config.h>
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#include <simobject.h>
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#include "uuid_gen.h"
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#include "debug.h"
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namespace vortex {
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typedef uint8_t Byte;
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#if XLEN == 32
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#if (XLEN == 32)
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typedef uint32_t Word;
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typedef int32_t WordI;
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typedef uint64_t DWord;
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typedef int64_t DWordI;
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#elif XLEN == 64
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typedef uint32_t WordF;
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#elif (XLEN == 64)
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typedef uint64_t Word;
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typedef int64_t WordI;
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typedef __uint128_t DWord;
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typedef __int128_t DWordI;
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typedef uint64_t WordF;
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#else
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#error unsupported XLEN
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#endif
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typedef uint64_t FWord;
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#define MAX_NUM_CORES 1024
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#define MAX_NUM_THREADS 32
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#define MAX_NUM_WARPS 32
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#define MAX_NUM_REGS 32
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typedef std::bitset<32> RegMask;
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typedef std::bitset<32> ThreadMask;
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typedef std::bitset<32> WarpMask;
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typedef std::bitset<MAX_NUM_CORES> CoreMask;
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typedef std::bitset<MAX_NUM_REGS> RegMask;
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typedef std::bitset<MAX_NUM_THREADS> ThreadMask;
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typedef std::bitset<MAX_NUM_WARPS> WarpMask;
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typedef std::unordered_map<uint32_t, uint32_t> CSRs;
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///////////////////////////////////////////////////////////////////////////////
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@@ -40,8 +64,8 @@ enum class RegType {
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Vector
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};
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inline std::ostream &operator<<(std::ostream &os, const RegType& clss) {
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switch (clss) {
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inline std::ostream &operator<<(std::ostream &os, const RegType& type) {
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switch (type) {
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case RegType::None: break;
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case RegType::Integer: os << "x"; break;
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case RegType::Float: os << "f"; break;
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@@ -53,23 +77,19 @@ inline std::ostream &operator<<(std::ostream &os, const RegType& clss) {
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///////////////////////////////////////////////////////////////////////////////
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enum class ExeType {
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NOP,
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ALU,
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LSU,
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CSR,
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FPU,
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GPU,
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SFU,
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MAX,
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};
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inline std::ostream &operator<<(std::ostream &os, const ExeType& type) {
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switch (type) {
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case ExeType::NOP: os << "NOP"; break;
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case ExeType::ALU: os << "ALU"; break;
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case ExeType::LSU: os << "LSU"; break;
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case ExeType::CSR: os << "CSR"; break;
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case ExeType::FPU: os << "FPU"; break;
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case ExeType::GPU: os << "GPU"; break;
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case ExeType::SFU: os << "SFU"; break;
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case ExeType::MAX: break;
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}
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return os;
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@@ -82,8 +102,7 @@ enum class AluType {
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BRANCH,
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SYSCALL,
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IMUL,
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IDIV,
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CMOV,
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IDIV
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};
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inline std::ostream &operator<<(std::ostream &os, const AluType& type) {
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@@ -93,7 +112,6 @@ inline std::ostream &operator<<(std::ostream &os, const AluType& type) {
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case AluType::SYSCALL: os << "SYSCALL"; break;
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case AluType::IMUL: os << "IMUL"; break;
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case AluType::IDIV: os << "IDIV"; break;
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case AluType::CMOV: os << "CMOV"; break;
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}
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return os;
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}
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@@ -103,16 +121,14 @@ inline std::ostream &operator<<(std::ostream &os, const AluType& type) {
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enum class LsuType {
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LOAD,
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STORE,
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FENCE,
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PREFETCH,
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FENCE
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};
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inline std::ostream &operator<<(std::ostream &os, const LsuType& type) {
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switch (type) {
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case LsuType::LOAD: os << "LOAD"; break;
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case LsuType::STORE: os << "STORE"; break;
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case LsuType::FENCE: os << "FENCE"; break;
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case LsuType::PREFETCH: os << "PREFETCH"; break;
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case LsuType::LOAD: os << "LOAD"; break;
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case LsuType::STORE: os << "STORE"; break;
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case LsuType::FENCE: os << "FENCE"; break;
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}
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return os;
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}
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@@ -141,21 +157,6 @@ struct mem_addr_size_t {
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uint32_t size;
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};
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inline AddrType get_addr_type(Word addr, uint32_t size) {
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__unused (size);
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if (SM_ENABLE) {
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if (addr >= (SMEM_BASE_ADDR - SMEM_SIZE)
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&& addr < SMEM_BASE_ADDR) {
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assert((addr + size) <= SMEM_BASE_ADDR);
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return AddrType::Shared;
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}
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}
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if (addr >= IO_BASE_ADDR) {
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return AddrType::IO;
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}
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return AddrType::Global;
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}
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///////////////////////////////////////////////////////////////////////////////
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enum class FpuType {
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@@ -179,23 +180,31 @@ inline std::ostream &operator<<(std::ostream &os, const FpuType& type) {
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///////////////////////////////////////////////////////////////////////////////
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enum class GpuType {
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enum class SfuType {
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TMC,
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WSPAWN,
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SPLIT,
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JOIN,
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BAR,
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TEX,
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PRED,
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CSRRW,
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CSRRS,
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CSRRC,
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CMOV
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};
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inline std::ostream &operator<<(std::ostream &os, const GpuType& type) {
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inline std::ostream &operator<<(std::ostream &os, const SfuType& type) {
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switch (type) {
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case GpuType::TMC: os << "TMC"; break;
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case GpuType::WSPAWN: os << "WSPAWN"; break;
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case GpuType::SPLIT: os << "SPLIT"; break;
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case GpuType::JOIN: os << "JOIN"; break;
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case GpuType::BAR: os << "BAR"; break;
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case GpuType::TEX: os << "TEX"; break;
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case SfuType::TMC: os << "TMC"; break;
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case SfuType::WSPAWN: os << "WSPAWN"; break;
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case SfuType::SPLIT: os << "SPLIT"; break;
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case SfuType::JOIN: os << "JOIN"; break;
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case SfuType::BAR: os << "BAR"; break;
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case SfuType::PRED: os << "PRED"; break;
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case SfuType::CSRRW: os << "CSRRW"; break;
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case SfuType::CSRRS: os << "CSRRS"; break;
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case SfuType::CSRRC: os << "CSRRC"; break;
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case SfuType::CMOV: os << "CMOV"; break;
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}
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return os;
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}
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@@ -218,31 +227,32 @@ inline std::ostream &operator<<(std::ostream &os, const ArbiterType& type) {
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///////////////////////////////////////////////////////////////////////////////
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struct MemReq {
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uint64_t addr;
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bool write;
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bool non_cacheable;
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uint32_t tag;
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uint32_t core_id;
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uint64_t uuid;
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uint64_t addr;
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bool write;
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AddrType type;
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uint32_t tag;
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uint32_t cid;
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uint64_t uuid;
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MemReq(uint64_t _addr = 0,
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bool _write = false,
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bool _non_cacheable = false,
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uint64_t _tag = 0,
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uint32_t _core_id = 0,
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uint64_t _uuid = 0
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) : addr(_addr)
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, write(_write)
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, non_cacheable(_non_cacheable)
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, tag(_tag)
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, core_id(_core_id)
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, uuid(_uuid)
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{}
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MemReq(uint64_t _addr = 0,
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bool _write = false,
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AddrType _type = AddrType::Global,
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uint64_t _tag = 0,
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uint32_t _cid = 0,
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uint64_t _uuid = 0
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) : addr(_addr)
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, write(_write)
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, type(_type)
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, tag(_tag)
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, cid(_cid)
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, uuid(_uuid)
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{}
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};
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inline std::ostream &operator<<(std::ostream &os, const MemReq& req) {
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os << "mem-" << (req.write ? "wr" : "rd") << ": ";
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os << "addr=" << std::hex << req.addr << std::dec << ", tag=" << req.tag << ", core_id=" << req.core_id;
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os << "addr=0x" << std::hex << req.addr << ", type=" << req.type;
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os << std::dec << ", tag=" << req.tag << ", cid=" << req.cid;
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os << " (#" << std::dec << req.uuid << ")";
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return os;
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}
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@@ -250,18 +260,19 @@ inline std::ostream &operator<<(std::ostream &os, const MemReq& req) {
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///////////////////////////////////////////////////////////////////////////////
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struct MemRsp {
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uint64_t tag;
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uint32_t core_id;
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uint64_t uuid;
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MemRsp(uint64_t _tag = 0, uint32_t _core_id = 0, uint64_t _uuid = 0)
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: tag (_tag)
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, core_id(_core_id)
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, uuid(_uuid)
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{}
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uint64_t tag;
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uint32_t cid;
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uint64_t uuid;
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MemRsp(uint64_t _tag = 0, uint32_t _cid = 0, uint64_t _uuid = 0)
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: tag (_tag)
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, cid(_cid)
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, uuid(_uuid)
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{}
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};
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inline std::ostream &operator<<(std::ostream &os, const MemRsp& rsp) {
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os << "mem-rsp: tag=" << rsp.tag << ", core_id=" << rsp.core_id;
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os << "mem-rsp: tag=" << rsp.tag << ", cid=" << rsp.cid;
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os << " (#" << std::dec << rsp.uuid << ")";
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return os;
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}
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@@ -270,10 +281,6 @@ inline std::ostream &operator<<(std::ostream &os, const MemRsp& rsp) {
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template <typename T>
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class HashTable {
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private:
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std::vector<std::pair<bool, T>> entries_;
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uint32_t size_;
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public:
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HashTable(uint32_t capacity)
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: entries_(capacity)
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@@ -336,92 +343,180 @@ public:
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}
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size_ = 0;
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}
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private:
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std::vector<std::pair<bool, T>> entries_;
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uint32_t size_;
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};
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///////////////////////////////////////////////////////////////////////////////
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template <typename Req, typename Rsp, uint32_t MaxInputs = 32>
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template <typename Req, typename Rsp>
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class Switch : public SimObject<Switch<Req, Rsp>> {
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private:
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ArbiterType type_;
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uint32_t delay_;
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uint32_t cursor_;
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uint32_t tag_shift_;
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public:
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std::vector<SimPort<Req>> ReqIn;
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std::vector<SimPort<Rsp>> RspIn;
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std::vector<SimPort<Req>> ReqOut;
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std::vector<SimPort<Rsp>> RspOut;
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Switch(
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const SimContext& ctx,
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const char* name,
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ArbiterType type,
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uint32_t num_inputs,
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uint32_t num_inputs = 1,
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uint32_t num_outputs = 1,
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uint32_t delay = 1
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)
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: SimObject<Switch<Req, Rsp, MaxInputs>>(ctx, name)
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: SimObject<Switch<Req, Rsp>>(ctx, name)
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, ReqIn(num_inputs, this)
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, RspIn(num_inputs, this)
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, ReqOut(num_outputs, this)
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, RspOut(num_outputs, this)
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, type_(type)
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, delay_(delay)
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, cursor_(0)
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, tag_shift_(log2ceil(num_inputs))
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, ReqIn(num_inputs, this)
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, ReqOut(this)
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, RspIn(this)
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, RspOut(num_inputs, this)
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, cursors_(num_outputs, 0)
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, lg_num_reqs_(log2ceil(num_inputs / num_outputs))
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{
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assert(delay_ != 0);
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assert(num_inputs <= MaxInputs);
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if (num_inputs == 1) {
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// bypass
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ReqIn.at(0).bind(&ReqOut);
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RspIn.bind(&RspOut.at(0));
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assert(delay != 0);
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assert(num_inputs <= 32);
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assert(num_outputs <= 32);
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assert(num_inputs >= num_outputs);
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if (num_inputs == num_outputs) {
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// bypass mode
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for (uint32_t i = 0; i < num_inputs; ++i) {
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ReqIn.at(i).bind(&ReqOut.at(i));
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RspOut.at(i).bind(&RspIn.at(i));
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}
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}
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}
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void reset() {
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cursor_ = 0;
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for (auto& cursor : cursors_) {
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cursor = 0;
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}
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}
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void tick() {
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if (ReqIn.size() == 1)
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void tick() {
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uint32_t I = ReqIn.size();
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uint32_t O = ReqOut.size();
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uint32_t R = 1 << lg_num_reqs_;
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// skip bypass mode
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if (I == O)
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return;
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// process incomming requests
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for (uint32_t i = 0, n = ReqIn.size(); i < n; ++i) {
|
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uint32_t j = (cursor_ + i) % n;
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auto& req_in = ReqIn.at(j);
|
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if (!req_in.empty()) {
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auto& req = req_in.front();
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if (tag_shift_) {
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req.tag = (req.tag << tag_shift_) | j;
|
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// process incomming requests
|
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for (uint32_t o = 0; o < O; ++o) {
|
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for (uint32_t r = 0; r < R; ++r) {
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uint32_t i = (cursors_.at(o) + r) & (R-1);
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||||
uint32_t j = o * R + i;
|
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if (j >= I)
|
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continue;
|
||||
|
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auto& req_in = ReqIn.at(j);
|
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if (!req_in.empty()) {
|
||||
auto& req = req_in.front();
|
||||
if (lg_num_reqs_ != 0) {
|
||||
req.tag = (req.tag << lg_num_reqs_) | i;
|
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}
|
||||
DT(4, this->name() << "-" << req);
|
||||
ReqOut.at(o).send(req, delay_);
|
||||
req_in.pop();
|
||||
this->update_cursor(o, i);
|
||||
break;
|
||||
}
|
||||
ReqOut.send(req, delay_);
|
||||
req_in.pop();
|
||||
this->update_cursor(j);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// process incoming reponses
|
||||
if (!RspIn.empty()) {
|
||||
auto& rsp = RspIn.front();
|
||||
uint32_t port_id = 0;
|
||||
if (tag_shift_) {
|
||||
port_id = rsp.tag & ((1 << tag_shift_)-1);
|
||||
rsp.tag >>= tag_shift_;
|
||||
}
|
||||
RspOut.at(port_id).send(rsp, 1);
|
||||
RspIn.pop();
|
||||
|
||||
// process incoming reponses
|
||||
if (!RspOut.at(o).empty()) {
|
||||
auto& rsp = RspOut.at(o).front();
|
||||
uint32_t i = 0;
|
||||
if (lg_num_reqs_ != 0) {
|
||||
i = rsp.tag & (R-1);
|
||||
rsp.tag >>= lg_num_reqs_;
|
||||
}
|
||||
DT(4, this->name() << "-" << rsp);
|
||||
uint32_t j = o * R + i;
|
||||
RspIn.at(j).send(rsp, 1);
|
||||
RspOut.at(o).pop();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void update_cursor(uint32_t grant) {
|
||||
void update_cursor(uint32_t index, uint32_t grant) {
|
||||
if (type_ == ArbiterType::RoundRobin) {
|
||||
cursor_ = grant + 1;
|
||||
cursors_.at(index) = grant + 1;
|
||||
}
|
||||
}
|
||||
|
||||
std::vector<SimPort<Req>> ReqIn;
|
||||
SimPort<Req> ReqOut;
|
||||
SimPort<Rsp> RspIn;
|
||||
std::vector<SimPort<Rsp>> RspOut;
|
||||
private:
|
||||
ArbiterType type_;
|
||||
uint32_t delay_;
|
||||
std::vector<uint32_t> cursors_;
|
||||
uint32_t lg_num_reqs_;
|
||||
};
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
class SMemDemux : public SimObject<SMemDemux> {
|
||||
public:
|
||||
SimPort<MemReq> ReqIn;
|
||||
SimPort<MemRsp> RspIn;
|
||||
|
||||
SimPort<MemReq> ReqSm;
|
||||
SimPort<MemRsp> RspSm;
|
||||
|
||||
SimPort<MemReq> ReqDc;
|
||||
SimPort<MemRsp> RspDc;
|
||||
|
||||
SMemDemux(
|
||||
const SimContext& ctx,
|
||||
const char* name,
|
||||
uint32_t delay = 1
|
||||
) : SimObject<SMemDemux>(ctx, name)
|
||||
, ReqIn(this)
|
||||
, RspIn(this)
|
||||
, ReqSm(this)
|
||||
, RspSm(this)
|
||||
, ReqDc(this)
|
||||
, RspDc(this)
|
||||
, delay_(delay)
|
||||
{}
|
||||
|
||||
void reset() {}
|
||||
|
||||
void tick() {
|
||||
// process incomming requests
|
||||
if (!ReqIn.empty()) {
|
||||
auto& req = ReqIn.front();
|
||||
DT(4, this->name() << "-" << req);
|
||||
if (req.type == AddrType::Shared) {
|
||||
ReqSm.send(req, delay_);
|
||||
} else {
|
||||
ReqDc.send(req, delay_);
|
||||
}
|
||||
ReqIn.pop();
|
||||
}
|
||||
|
||||
// process incoming reponses
|
||||
if (!RspSm.empty()) {
|
||||
auto& rsp = RspSm.front();
|
||||
DT(4, this->name() << "-" << rsp);
|
||||
RspIn.send(rsp, 1);
|
||||
RspSm.pop();
|
||||
}
|
||||
if (!RspDc.empty()) {
|
||||
auto& rsp = RspDc.front();
|
||||
DT(4, this->name() << "-" << rsp);
|
||||
RspIn.send(rsp, 1);
|
||||
RspDc.pop();
|
||||
}
|
||||
}
|
||||
|
||||
private:
|
||||
uint32_t delay_;
|
||||
};
|
||||
|
||||
}
|
||||
Reference in New Issue
Block a user