Vortex 2.0 changes:
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
This commit is contained in:
Blaise Tine
@@ -1,168 +1,141 @@
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// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "processor.h"
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#include "core.h"
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#include "constants.h"
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#include "processor_impl.h"
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using namespace vortex;
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class Processor::Impl {
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private:
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std::vector<Core::Ptr> cores_;
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std::vector<Cache::Ptr> l2caches_;
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std::vector<Switch<MemReq, MemRsp>::Ptr> l2_mem_switches_;
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Cache::Ptr l3cache_;
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Switch<MemReq, MemRsp>::Ptr l3_mem_switch_;
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ProcessorImpl::ProcessorImpl(const Arch& arch)
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: arch_(arch)
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, clusters_(arch.num_clusters())
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{
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SimPlatform::instance().initialize();
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public:
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Impl(const ArchDef& arch)
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: cores_(arch.num_cores())
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, l2caches_(NUM_CLUSTERS)
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, l2_mem_switches_(NUM_CLUSTERS)
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{
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SimPlatform::instance().initialize();
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// create memory simulator
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memsim_ = MemSim::Create("dram", MemSim::Config{
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MEMORY_BANKS,
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uint32_t(arch.num_cores()) * arch.num_clusters()
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});
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uint32_t num_cores = arch.num_cores();
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uint32_t cores_per_cluster = num_cores / NUM_CLUSTERS;
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// create cores
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for (uint32_t i = 0; i < num_cores; ++i) {
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cores_.at(i) = Core::Create(arch, i);
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// create L3 cache
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l3cache_ = CacheSim::Create("l3cache", CacheSim::Config{
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!L3_ENABLED,
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log2ceil(L3_CACHE_SIZE), // C
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log2ceil(MEM_BLOCK_SIZE), // B
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log2ceil(L3_NUM_WAYS), // W
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0, // A
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XLEN, // address bits
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L3_NUM_BANKS, // number of banks
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1, // number of ports
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uint8_t(arch.num_clusters()), // request size
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true, // write-through
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false, // write response
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0, // victim size
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L3_MSHR_SIZE, // mshr
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2, // pipeline latency
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}
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);
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// connect L3 memory ports
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l3cache_->MemReqPort.bind(&memsim_->MemReqPort);
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memsim_->MemRspPort.bind(&l3cache_->MemRspPort);
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// setup memory simulator
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auto memsim = MemSim::Create("dram", MemSim::Config{
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MEMORY_BANKS,
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arch.num_cores()
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});
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std::vector<SimPort<MemReq>*> mem_req_ports(1, &memsim->MemReqPort);
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std::vector<SimPort<MemRsp>*> mem_rsp_ports(1, &memsim->MemRspPort);
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if (L3_ENABLE) {
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l3cache_ = Cache::Create("l3cache", Cache::Config{
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log2ceil(L3_CACHE_SIZE), // C
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log2ceil(MEM_BLOCK_SIZE), // B
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2, // W
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0, // A
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32, // address bits
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L3_NUM_BANKS, // number of banks
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L3_NUM_PORTS, // number of ports
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NUM_CLUSTERS, // request size
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true, // write-through
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false, // write response
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0, // victim size
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L3_MSHR_SIZE, // mshr
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2, // pipeline latency
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}
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);
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l3cache_->MemReqPort.bind(mem_req_ports.at(0));
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mem_rsp_ports.at(0)->bind(&l3cache_->MemRspPort);
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mem_req_ports.resize(NUM_CLUSTERS);
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mem_rsp_ports.resize(NUM_CLUSTERS);
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for (uint32_t i = 0; i < NUM_CLUSTERS; ++i) {
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mem_req_ports.at(i) = &l3cache_->CoreReqPorts.at(i);
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mem_rsp_ports.at(i) = &l3cache_->CoreRspPorts.at(i);
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}
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} else if (NUM_CLUSTERS > 1) {
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l3_mem_switch_ = Switch<MemReq, MemRsp>::Create("l3_arb", ArbiterType::RoundRobin, NUM_CLUSTERS);
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l3_mem_switch_->ReqOut.bind(mem_req_ports.at(0));
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mem_rsp_ports.at(0)->bind(&l3_mem_switch_->RspIn);
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mem_req_ports.resize(NUM_CLUSTERS);
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mem_rsp_ports.resize(NUM_CLUSTERS);
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for (uint32_t i = 0; i < NUM_CLUSTERS; ++i) {
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mem_req_ports.at(i) = &l3_mem_switch_->ReqIn.at(i);
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mem_rsp_ports.at(i) = &l3_mem_switch_->RspOut.at(i);
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}
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}
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for (uint32_t i = 0; i < NUM_CLUSTERS; ++i) {
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std::vector<SimPort<MemReq>*> cluster_mem_req_ports(cores_per_cluster);
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std::vector<SimPort<MemRsp>*> cluster_mem_rsp_ports(cores_per_cluster);
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if (L2_ENABLE) {
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auto& l2cache = l2caches_.at(i);
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l2cache = Cache::Create("l2cache", Cache::Config{
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log2ceil(L2_CACHE_SIZE), // C
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log2ceil(MEM_BLOCK_SIZE), // B
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2, // W
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0, // A
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32, // address bits
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L2_NUM_BANKS, // number of banks
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L2_NUM_PORTS, // number of ports
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(uint8_t)cores_per_cluster, // request size
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true, // write-through
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false, // write response
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0, // victim size
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L2_MSHR_SIZE, // mshr
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2, // pipeline latency
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});
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l2cache->MemReqPort.bind(mem_req_ports.at(i));
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mem_rsp_ports.at(i)->bind(&l2cache->MemRspPort);
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for (uint32_t j = 0; j < cores_per_cluster; ++j) {
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cluster_mem_req_ports.at(j) = &l2cache->CoreReqPorts.at(j);
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cluster_mem_rsp_ports.at(j) = &l2cache->CoreRspPorts.at(j);
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}
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} else {
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auto& l2_mem_switch = l2_mem_switches_.at(i);
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l2_mem_switch = Switch<MemReq, MemRsp>::Create("l2_arb", ArbiterType::RoundRobin, cores_per_cluster);
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l2_mem_switch->ReqOut.bind(mem_req_ports.at(i));
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mem_rsp_ports.at(i)->bind(&l2_mem_switch->RspIn);
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for (uint32_t j = 0; j < cores_per_cluster; ++j) {
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cluster_mem_req_ports.at(j) = &l2_mem_switch->ReqIn.at(j);
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cluster_mem_rsp_ports.at(j) = &l2_mem_switch->RspOut.at(j);
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}
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}
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for (uint32_t j = 0; j < cores_per_cluster; ++j) {
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auto& core = cores_.at((i * cores_per_cluster) + j);
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core->MemReqPort.bind(cluster_mem_req_ports.at(j));
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cluster_mem_rsp_ports.at(j)->bind(&core->MemRspPort);
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}
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}
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// create clusters
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for (uint32_t i = 0; i < arch.num_clusters(); ++i) {
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clusters_.at(i) = Cluster::Create(i, this, arch, dcrs_);
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// connect L3 core ports
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clusters_.at(i)->mem_req_port.bind(&l3cache_->CoreReqPorts.at(i));
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l3cache_->CoreRspPorts.at(i).bind(&clusters_.at(i)->mem_rsp_port);
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}
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~Impl() {
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SimPlatform::instance().finalize();
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}
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// set up memory perf recording
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memsim_->MemReqPort.tx_callback([&](const MemReq& req, uint64_t cycle){
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__unused (cycle);
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perf_mem_reads_ += !req.write;
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perf_mem_writes_ += req.write;
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perf_mem_pending_reads_ += !req.write;
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});
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memsim_->MemRspPort.tx_callback([&](const MemRsp&, uint64_t cycle){
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__unused (cycle);
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--perf_mem_pending_reads_;
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});
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void attach_ram(RAM* ram) {
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for (auto core : cores_) {
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core->attach_ram(ram);
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}
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}
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this->reset();
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}
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int run() {
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SimPlatform::instance().reset();
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bool running;
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int exitcode = 0;
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do {
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SimPlatform::instance().tick();
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running = false;
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for (auto& core : cores_) {
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if (core->running()) {
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running = true;
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}
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if (core->check_exit()) {
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exitcode = core->getIRegValue(3);
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running = false;
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break;
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ProcessorImpl::~ProcessorImpl() {
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SimPlatform::instance().finalize();
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}
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void ProcessorImpl::attach_ram(RAM* ram) {
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for (auto cluster : clusters_) {
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cluster->attach_ram(ram);
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}
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}
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int ProcessorImpl::run(bool riscv_test) {
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SimPlatform::instance().reset();
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this->reset();
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bool done;
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Word exitcode = 0;
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do {
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SimPlatform::instance().tick();
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done = true;
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for (auto cluster : clusters_) {
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if (cluster->running()) {
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Word ec;
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if (cluster->check_exit(&ec, riscv_test)) {
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exitcode |= ec;
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} else {
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done = false;
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}
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}
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} while (running);
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}
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perf_mem_latency_ += perf_mem_pending_reads_;
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} while (!done);
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return exitcode;
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}
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};
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return exitcode;
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}
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void ProcessorImpl::reset() {
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perf_mem_reads_ = 0;
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perf_mem_writes_ = 0;
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perf_mem_latency_ = 0;
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perf_mem_pending_reads_ = 0;
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}
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void ProcessorImpl::write_dcr(uint32_t addr, uint32_t value) {
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dcrs_.write(addr, value);
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}
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ProcessorImpl::PerfStats ProcessorImpl::perf_stats() const {
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ProcessorImpl::PerfStats perf;
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perf.mem_reads = perf_mem_reads_;
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perf.mem_writes = perf_mem_writes_;
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perf.mem_latency = perf_mem_latency_;
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perf.l3cache = l3cache_->perf_stats();
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for (auto cluster : clusters_) {
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perf.clusters += cluster->perf_stats();
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}
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return perf;
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}
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///////////////////////////////////////////////////////////////////////////////
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Processor::Processor(const ArchDef& arch)
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: impl_(new Impl(arch))
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Processor::Processor(const Arch& arch)
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: impl_(new ProcessorImpl(arch))
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{}
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Processor::~Processor() {
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@@ -173,6 +146,10 @@ void Processor::attach_ram(RAM* mem) {
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impl_->attach_ram(mem);
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}
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int Processor::run() {
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return impl_->run();
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int Processor::run(bool riscv_test) {
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return impl_->run(riscv_test);
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}
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void Processor::write_dcr(uint32_t addr, uint32_t value) {
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return impl_->write_dcr(addr, value);
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}
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