Vortex 2.0 changes:
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
This commit is contained in:
Blaise Tine
149
sim/simx/core.h
149
sim/simx/core.h
@@ -1,3 +1,16 @@
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// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#include <string>
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@@ -11,101 +24,104 @@
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#include <simobject.h>
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#include "debug.h"
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#include "types.h"
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#include "archdef.h"
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#include "arch.h"
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#include "decode.h"
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#include "mem.h"
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#include "warp.h"
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#include "pipeline.h"
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#include "cache.h"
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#include "sharedmem.h"
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#include "cache_sim.h"
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#include "shared_mem.h"
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#include "ibuffer.h"
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#include "scoreboard.h"
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#include "exeunit.h"
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#include "tex_unit.h"
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#include "operand.h"
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#include "dispatcher.h"
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#include "exe_unit.h"
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#include "dcrs.h"
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namespace vortex {
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class Cluster;
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class Core : public SimObject<Core> {
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public:
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struct PerfStats {
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uint64_t cycles;
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uint64_t instrs;
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uint64_t ibuf_stalls;
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uint64_t scrb_stalls;
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uint64_t alu_stalls;
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uint64_t lsu_stalls;
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uint64_t csr_stalls;
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uint64_t fpu_stalls;
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uint64_t gpu_stalls;
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uint64_t sfu_stalls;
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uint64_t ifetches;
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uint64_t loads;
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uint64_t stores;
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uint64_t branches;
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uint64_t mem_reads;
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uint64_t mem_writes;
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uint64_t mem_latency;
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uint64_t tex_reads;
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uint64_t tex_latency;
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uint64_t ifetch_latency;
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uint64_t load_latency;
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PerfStats()
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: instrs(0)
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: cycles(0)
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, instrs(0)
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, ibuf_stalls(0)
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, scrb_stalls(0)
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, alu_stalls(0)
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, lsu_stalls(0)
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, csr_stalls(0)
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, fpu_stalls(0)
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, gpu_stalls(0)
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, sfu_stalls(0)
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, ifetches(0)
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, loads(0)
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, stores(0)
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, branches(0)
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, mem_reads(0)
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, mem_writes(0)
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, mem_latency(0)
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, tex_reads(0)
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, tex_latency(0)
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, ifetch_latency(0)
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, load_latency(0)
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{}
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};
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SimPort<MemRsp> MemRspPort;
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SimPort<MemReq> MemReqPort;
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std::vector<SimPort<MemReq>> icache_req_ports;
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std::vector<SimPort<MemRsp>> icache_rsp_ports;
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std::vector<SimPort<MemReq>> dcache_req_ports;
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std::vector<SimPort<MemRsp>> dcache_rsp_ports;
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Core(const SimContext& ctx,
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uint32_t core_id,
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Cluster* cluster,
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const Arch &arch,
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const DCRS &dcrs,
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SharedMem::Ptr sharedmem);
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Core(const SimContext& ctx, const ArchDef &arch, uint32_t id);
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~Core();
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void attach_ram(RAM* ram);
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bool running() const;
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void reset();
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void tick();
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void attach_ram(RAM* ram);
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bool running() const;
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void resume();
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uint32_t id() const {
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return id_;
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return core_id_;
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}
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const Decoder& decoder() {
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return decoder_;
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}
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const ArchDef& arch() const {
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const Arch& arch() const {
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return arch_;
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}
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const PerfStats& perf_stats() const {
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return perf_stats_;
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}
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uint32_t getIRegValue(int reg) const {
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return warps_.at(0)->getIRegValue(reg);
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const DCRS& dcrs() const {
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return dcrs_;
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}
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uint32_t get_csr(uint32_t addr, uint32_t tid, uint32_t wid);
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void set_csr(uint32_t addr, uint32_t value, uint32_t tid, uint32_t wid);
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WarpMask wspawn(uint32_t num_warps, uint32_t nextPC);
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void wspawn(uint32_t num_warps, Word nextPC);
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WarpMask barrier(uint32_t bar_id, uint32_t count, uint32_t warp_id);
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void barrier(uint32_t bar_id, uint32_t count, uint32_t warp_id);
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AddrType get_addr_type(uint64_t addr);
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void icache_read(void* data, uint64_t addr, uint32_t size);
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@@ -113,19 +129,22 @@ public:
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void dcache_write(const void* data, uint64_t addr, uint32_t size);
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uint32_t tex_read(uint32_t unit, uint32_t lod, uint32_t u, uint32_t v, std::vector<mem_addr_size_t>* mem_addrs);
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void dcache_amo_reserve(uint64_t addr);
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bool dcache_amo_check(uint64_t addr);
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void trigger_ecall();
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void trigger_ebreak();
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bool check_exit() const;
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bool check_exit(Word* exitcode, bool riscv_test) const;
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private:
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void schedule();
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void fetch();
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void decode();
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void issue();
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void execute();
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void commit();
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@@ -133,49 +152,51 @@ private:
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void cout_flush();
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uint32_t id_;
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const ArchDef arch_;
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uint32_t core_id_;
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const Arch& arch_;
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const DCRS &dcrs_;
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const Decoder decoder_;
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MemoryUnit mmu_;
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RAM smem_;
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std::vector<TexUnit> tex_units_;
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std::vector<std::shared_ptr<Warp>> warps_;
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std::vector<WarpMask> barriers_;
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std::vector<uint32_t> csrs_;
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std::vector<WarpMask> barriers_;
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std::vector<Byte> fcsrs_;
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std::vector<IBuffer> ibuffers_;
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Scoreboard scoreboard_;
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std::vector<Operand::Ptr> operands_;
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std::vector<Dispatcher::Ptr> dispatchers_;
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std::vector<ExeUnit::Ptr> exe_units_;
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Cache::Ptr icache_;
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Cache::Ptr dcache_;
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SharedMem::Ptr shared_mem_;
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Switch<MemReq, MemRsp>::Ptr l1_mem_switch_;
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std::vector<Switch<MemReq, MemRsp>::Ptr> dcache_switch_;
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SharedMem::Ptr sharedmem_;
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PipelineLatch fetch_latch_;
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PipelineLatch decode_latch_;
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HashTable<pipeline_trace_t*> pending_icache_;
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std::vector<pipeline_trace_t*> committed_traces_;
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WarpMask active_warps_;
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WarpMask stalled_warps_;
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uint32_t last_schedule_wid_;
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uint64_t issued_instrs_;
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uint64_t committed_instrs_;
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uint32_t csr_tex_unit_;
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bool ecall_;
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bool ebreak_;
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bool exited_;
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uint64_t pending_ifetches_;
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std::unordered_map<int, std::stringstream> print_bufs_;
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std::vector<std::vector<CSRs>> csrs_;
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PerfStats perf_stats_;
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uint64_t perf_mem_pending_reads_;
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Cluster* cluster_;
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uint32_t commit_exe_;
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friend class Warp;
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friend class LsuUnit;
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friend class AluUnit;
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friend class CsrUnit;
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friend class FpuUnit;
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friend class GpuUnit;
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friend class SfuUnit;
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};
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} // namespace vortex
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} // namespace vortex
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