Vortex 2.0 changes:
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
This commit is contained in:
Blaise Tine
227
kernel/include/vx_intrinsics.h
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227
kernel/include/vx_intrinsics.h
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// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef __VX_INTRINSICS_H__
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#define __VX_INTRINSICS_H__
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#include <VX_config.h>
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#include <VX_types.h>
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#if defined(__clang__)
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#define __UNIFORM__ __attribute__((annotate("vortex.uniform")))
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#else
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#define __UNIFORM__
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef __ASSEMBLY__
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#define __ASM_STR(x) x
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#else
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#define __ASM_STR(x) #x
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#endif
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#define RISCV_CUSTOM0 0x0B
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#define RISCV_CUSTOM1 0x2B
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#define RISCV_CUSTOM2 0x5B
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#define RISCV_CUSTOM3 0x7B
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#define csr_read(csr) ({ \
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unsigned __r; \
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__asm__ __volatile__ ("csrr %0, %1" : "=r" (__r) : "i" (csr)); \
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__r; \
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})
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#define csr_write(csr, val) ({ \
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unsigned __v = (unsigned)(val); \
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if (__builtin_constant_p(val) && __v < 32) \
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__asm__ __volatile__ ("csrw %0, %1" :: "i" (csr), "i" (__v)); \
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else \
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__asm__ __volatile__ ("csrw %0, %1" :: "i" (csr), "r" (__v)); \
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})
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#define csr_swap(csr, val) ({ \
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unsigned __r; \
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unsigned __v = (unsigned)(val); \
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if (__builtin_constant_p(val) && __v < 32) \
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__asm__ __volatile__ ("csrrw %0, %1, %2" : "=r" (__r) : "i" (csr), "i" (__v)); \
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else \
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__asm__ __volatile__ ("csrrw %0, %1, %2" : "=r" (__r) : "i" (csr), "r" (__v)); \
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__r; \
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})
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#define csr_read_set(csr, val) ({ \
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unsigned __r; \
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unsigned __v = (unsigned)(val); \
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if (__builtin_constant_p(val) && __v < 32) \
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__asm__ __volatile__ ("csrrs %0, %1, %2" : "=r" (__r) : "i" (csr), "i" (__v)); \
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else \
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__asm__ __volatile__ ("csrrs %0, %1, %2" : "=r" (__r) : "i" (csr), "r" (__v)); \
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__r; \
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})
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#define csr_set(csr, val) ({ \
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unsigned __v = (unsigned)(val); \
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if (__builtin_constant_p(val) && __v < 32) \
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__asm__ __volatile__ ("csrs %0, %1" :: "i" (csr), "i" (__v)); \
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else \
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__asm__ __volatile__ ("csrs %0, %1" :: "i" (csr), "r" (__v)); \
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})
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#define csr_read_clear(csr, val) ({ \
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unsigned __r; \
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unsigned __v = (unsigned)(val); \
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if (__builtin_constant_p(val) && __v < 32) \
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__asm__ __volatile__ ("csrrc %0, %1, %2" : "=r" (__r) : "i" (csr), "i" (__v)); \
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else \
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__asm__ __volatile__ ("csrrc %0, %1, %2" : "=r" (__r) : "i" (csr), "r" (__v)); \
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__r; \
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})
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#define csr_clear(csr, val) ({ \
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unsigned __v = (unsigned)(val); \
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if (__builtin_constant_p(val) && __v < 32) \
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__asm__ __volatile__ ("csrc %0, %1" :: "i" (csr), "i" (__v)); \
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else \
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__asm__ __volatile__ ("csrc %0, %1" :: "i" (csr), "r" (__v)); \
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})
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// Conditional move
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inline unsigned vx_cmov(unsigned c, unsigned t, unsigned f) {
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unsigned ret;
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asm volatile (".insn r4 %1, 1, 0, %0, %2, %3, %4" : "=r"(ret) : "i"(RISCV_CUSTOM1), "r"(c), "r"(t), "r"(f));
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return ret;
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}
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// Set thread mask
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inline void vx_tmc(unsigned thread_mask) {
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asm volatile (".insn r %0, 0, 0, x0, %1, x0" :: "i"(RISCV_CUSTOM0), "r"(thread_mask));
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}
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// disable all threads in the current warp
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inline void vx_tmc_zero() {
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asm volatile (".insn r %0, 0, 0, x0, x0, x0" :: "i"(RISCV_CUSTOM0));
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}
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// switch execution to single thread zero
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inline void vx_tmc_one() {
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asm volatile (
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"li a0, 1\n\t" // Load immediate value 1 into a0 (x10) register
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".insn r %0, 0, 0, x0, a0, x0" :: "i"(RISCV_CUSTOM0)
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: "a0" // Indicate that a0 (x10) is clobbered
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);
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}
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// Set thread predicate
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inline void vx_pred(unsigned condition, unsigned thread_mask) {
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asm volatile (".insn r %0, 5, 0, x0, %1, %2" :: "i"(RISCV_CUSTOM0), "r"(condition), "r"(thread_mask));
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}
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typedef void (*vx_wspawn_pfn)();
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// Spawn warps
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inline void vx_wspawn(unsigned num_warps, vx_wspawn_pfn func_ptr) {
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asm volatile (".insn r %0, 1, 0, x0, %1, %2" :: "i"(RISCV_CUSTOM0), "r"(num_warps), "r"(func_ptr));
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}
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// Split on a predicate
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inline unsigned vx_split(unsigned predicate) {
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unsigned ret;
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asm volatile (".insn r %1, 2, 0, %0, %2, x0" : "=r"(ret) : "i"(RISCV_CUSTOM0), "r"(predicate));
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return ret;
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}
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// Join
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inline void vx_join(unsigned stack_ptr) {
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asm volatile (".insn r %0, 3, 0, x0, %1, x0" :: "i"(RISCV_CUSTOM0), "r"(stack_ptr));
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}
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// Warp Barrier
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inline void vx_barrier(unsigned barried_id, unsigned num_warps) {
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asm volatile (".insn r %0, 4, 0, x0, %1, %2" :: "i"(RISCV_CUSTOM0), "r"(barried_id), "r"(num_warps));
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}
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// Return current thread identifier
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inline int vx_thread_id() {
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int ret;
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asm volatile ("csrr %0, %1" : "=r"(ret) : "i"(VX_CSR_THREAD_ID));
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return ret;
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}
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// Return current warp identifier
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inline int vx_warp_id() {
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int ret;
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asm volatile ("csrr %0, %1" : "=r"(ret) : "i"(VX_CSR_WARP_ID));
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return ret;
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}
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// Return current core identifier
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inline int vx_core_id() {
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int ret;
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asm volatile ("csrr %0, %1" : "=r"(ret) : "i"(VX_CSR_CORE_ID));
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return ret;
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}
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// Return current thread mask
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inline int vx_thread_mask() {
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int ret;
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asm volatile ("csrr %0, %1" : "=r"(ret) : "i"(VX_CSR_THREAD_MASK));
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return ret;
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}
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// Return number of active warps
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inline int vx_active_warps() {
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int ret;
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asm volatile ("csrr %0, %1" : "=r"(ret) : "i"(VX_CSR_WARP_MASK));
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return ret;
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}
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// Return the number of threads per warp
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inline int vx_num_threads() {
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int ret;
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asm volatile ("csrr %0, %1" : "=r"(ret) : "i"(VX_CSR_NUM_THREADS));
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return ret;
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}
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// Return the number of warps per core
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inline int vx_num_warps() {
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int ret;
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asm volatile ("csrr %0, %1" : "=r"(ret) : "i"(VX_CSR_NUM_WARPS));
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return ret;
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}
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// Return the number of cores per cluster
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inline int vx_num_cores() {
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int ret;
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asm volatile ("csrr %0, %1" : "=r"(ret) : "i"(VX_CSR_NUM_CORES));
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return ret;
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}
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// Return the hart identifier (thread id accross the processor)
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inline int vx_hart_id() {
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int ret;
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asm volatile ("csrr %0, %1" : "=r"(ret) : "i"(VX_CSR_MHARTID));
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return ret;
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}
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inline void vx_fence() {
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asm volatile ("fence iorw, iorw");
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}
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#ifdef __cplusplus
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}
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#endif
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#endif // __VX_INTRINSICS_H__
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34
kernel/include/vx_print.h
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34
kernel/include/vx_print.h
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// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef __VX_PRINT_H__
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#define __VX_PRINT_H__
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#include <stdarg.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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int vx_vprintf(const char* format, va_list va);
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int vx_printf(const char * format, ...);
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void vx_putchar(int c);
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void vx_putint(int value, int base);
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void vx_putfloat(float value, int precision);
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#ifdef __cplusplus
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}
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#endif
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#endif // __VX_PRINT_H__
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58
kernel/include/vx_spawn.h
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58
kernel/include/vx_spawn.h
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// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef __VX_SPAWN_H__
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#define __VX_SPAWN_H__
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#include <stdint.h>
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#include <stdio.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef struct {
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uint32_t num_groups[3];
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uint32_t global_offset[3];
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uint32_t local_size[3];
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char * printf_buffer;
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uint32_t *printf_buffer_position;
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uint32_t printf_buffer_capacity;
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uint32_t work_dim;
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} context_t;
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typedef void (*vx_spawn_kernel_cb) (
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const void * /* arg */,
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const context_t * /* context */,
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uint32_t /* group_x */,
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uint32_t /* group_y */,
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uint32_t /* group_z */
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);
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typedef void (*vx_spawn_tasks_cb)(int task_id, void *arg);
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typedef void (*vx_serial_cb)(void *arg);
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void vx_wspawn_wait();
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void vx_spawn_kernel(context_t * ctx, vx_spawn_kernel_cb callback, void * arg);
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void vx_spawn_tasks(int num_tasks, vx_spawn_tasks_cb callback, void * arg);
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void vx_serial(vx_serial_cb callback, void * arg);
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#ifdef __cplusplus
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}
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#endif
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#endif // __VX_SPAWN_H__
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