Vortex 2.0 changes:
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
This commit is contained in:
Blaise Tine
65
hw/unittest/mem_streamer/Makefile
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65
hw/unittest/mem_streamer/Makefile
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@@ -0,0 +1,65 @@
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DESTDIR ?= .
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RTL_DIR = ../../rtl
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DPI_DIR = ../../dpi
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CONFIGS +=
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PARAMS +=
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CXXFLAGS += -std=c++11 -Wall -Wextra -Wfatal-errors -Wno-array-bounds
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CXXFLAGS += -fPIC -Wno-maybe-uninitialized
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CXXFLAGS += -I../../.. -I../../common -I../../../../sim/common
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CXXFLAGS += $(CONFIGS)
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LDFLAGS +=
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DBG_FLAGS += -DDEBUG_LEVEL=$(DEBUG) -DVCD_OUTPUT $(DBG_TRACE_FLAGS)
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RTL_PKGS +=
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RTL_INCLUDE = -I$(RTL_DIR) -I$(DPI_DIR) -I$(RTL_DIR)/libs
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SRCS = memsim.cpp ram.cpp
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SRCS += $(DPI_DIR)/util_dpi.cpp
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TOP = VX_mem_scheduler
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VL_FLAGS = --exe
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VL_FLAGS += --language 1800-2009 --assert -Wall -Wpedantic
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VL_FLAGS += -Wno-DECLFILENAME -Wno-REDEFMACRO
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VL_FLAGS += --x-initial unique --x-assign unique
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VL_FLAGS += -DSIMULATION
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VL_FLAGS += $(CONFIGS)
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VL_FLAGS += $(PARAMS)
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VL_FLAGS += $(RTL_INCLUDE)
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VL_FLAGS += $(RTL_PKGS)
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VL_FLAGS += --cc $(TOP) --top-module $(TOP)
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# Enable Verilator multithreaded simulation
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THREADS ?= $(shell python -c 'import multiprocessing as mp; print(mp.cpu_count())')
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VL_FLAGS += -j $(THREADS)
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#VL_FLAGS += --threads $(THREADS)
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# Debugigng
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ifdef DEBUG
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VL_FLAGS += --trace --trace-structs $(DBG_FLAGS)
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CXXFLAGS += -g -O0 $(DBG_FLAGS)
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else
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VL_FLAGS += -DNDEBUG
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CXXFLAGS += -O2 -DNDEBUG
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endif
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PROJECT = mem_streamer
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all: $(DESTDIR)/$(PROJECT)
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$(DESTDIR)/$(PROJECT): $(SRCS)
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verilator --build $(VL_FLAGS) $^ -CFLAGS '$(CXXFLAGS)' -o ../$@
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run: $(DESTDIR)/$(PROJECT)
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$(DESTDIR)/$(PROJECT)
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waves: trace.vcd
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gtkwave -o trace.vcd
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clean:
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rm -rf obj_dir $(DESTDIR)/$(PROJECT)
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166
hw/unittest/mem_streamer/memsim.cpp
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166
hw/unittest/mem_streamer/memsim.cpp
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@@ -0,0 +1,166 @@
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// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <random>
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#include "memsim.h"
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#include "ram.h"
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#ifndef TRACE_START_TIME
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#define TRACE_START_TIME 0ull
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#endif
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#ifndef TRACE_STOP_TIME
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#define TRACE_STOP_TIME -1ull
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#endif
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static bool trace_enabled = false;
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static uint64_t trace_start_time = 0;
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static uint64_t trace_stop_time = -1ull;
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static uint64_t timestamp = 0;
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double sc_time_stamp() {
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return timestamp;
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}
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bool sim_trace_enabled() {
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if (timestamp >= trace_start_time
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&& timestamp < trace_stop_time)
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return true;
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return trace_enabled;
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}
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void sim_trace_enable (bool enable) {
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trace_enabled = enable;
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}
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int generate_rand (int min, int max) {
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int range = max - min + 1;
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return rand() % range + min;
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}
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int generate_rand_mask (int mask) {
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int result = 0;
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int m = mask;
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for (int i = 0; i < 4; i++) {
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int bit = m & 0b1;
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int rand_bit = generate_rand (0, bit);
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result |= (rand_bit << i);
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m = m >> 1;
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}
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return result;
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}
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MemSim::MemSim() {
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msu_ = new VVX_mem_scheduler();
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// Enable tracing
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Verilated::traceEverOn(true);
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#ifdef VCD_OUTPUT
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Verilated::traceEverOn(true);
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trace_ = new VerilatedVcdC;
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cache_->trace(trace_, 99);
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race_->open("trace.vcd");
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#endif
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}
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MemSim::~MemSim() {
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#ifdef VCD_OUTPUT
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trace_->close();
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#endif
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delete msu_;
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}
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void MemSim::eval() {
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msu_->eval();
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#ifdef VCD_OUTPUT
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trace_->dump(timestamp++);
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#endif
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}
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void MemSim::step() {
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msu_->clk = 0;
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this->eval();
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msu_->clk = 1;
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this->eval();
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}
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void MemSim::reset() {
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msu_->reset = 1;
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this->step();
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msu_->reset = 0;
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this->step();
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}
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void MemSim::attach_core() {
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if (msu_->req_ready) {
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msu_->req_valid = generate_rand(0, 1);
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msu_->req_rw = generate_rand(0, 1);
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msu_->req_mask = generate_rand(0b0001, 0b1111);
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msu_->req_byteen = 0b1;
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msu_->req_addr = generate_rand(0, 0x10000000);
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msu_->req_data = generate_rand(0x60000000, 0x80000000);
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msu_->req_tag = generate_rand(0x00, 0xFF);
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}
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msu_->rsp_ready = true;
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}
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void MemSim::attach_ram (RAM *ram) {
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req_t req;
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req.valid = msu_->mem_req_valid;
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req.rw = msu_->mem_req_rw;
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req.byteen = msu_->mem_req_byteen;
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req.addr = msu_->mem_req_addr;
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req.data = msu_->mem_req_data;
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req.tag = msu_->mem_req_tag;
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msu_->mem_req_ready = ram->is_ready();
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ram->insert_req(req);
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rsp_t rsp;
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rsp = ram->schedule_rsp();
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msu_->mem_rsp_valid = rsp.valid;
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msu_->mem_rsp_data = rsp.data;
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msu_->mem_rsp_tag = rsp.tag;
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rsp.ready = msu_->mem_rsp_ready;
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std::cout<<"MEMSIM: mem_rsp_ready: "<<rsp.ready<<"\n";
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ram->halt_rsp(rsp);
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}
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void MemSim::run(RAM *ram) {
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this->reset();
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while (sc_time_stamp() < SIM_TIME) {
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this->step();
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std::cout<<"========================="<<"\n";
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std::cout<<"Cycle: "<<sc_time_stamp()<<"\n";
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this->attach_core();
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this->attach_ram(ram);
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}
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}
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int main (int argc, char** argv, char** env) {
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Verilated::commandArgs(argc, argv);
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MemSim memsim;
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RAM ram;
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memsim.run(&ram);
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return 0;
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}
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49
hw/unittest/mem_streamer/memsim.h
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49
hw/unittest/mem_streamer/memsim.h
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@@ -0,0 +1,49 @@
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// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#include <iostream>
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#include <unordered_map>
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#include <vector>
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#include <verilated.h>
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#include <verilated_vcd_c.h>
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#include "VVX_mem_scheduler.h"
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#include "VVX_mem_scheduler__Syms.h"
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#include "ram.h"
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#define SIM_TIME 5000
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int generate_rand (int min, int max);
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int generate_rand_mask (int mask);
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class MemSim {
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public:
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MemSim();
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virtual ~MemSim();
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void run(RAM *ram);
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private:
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VVX_mem_scheduler *msu_;
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#ifdef VCD_OUTPUT
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VerilatedVcdC *trace_;
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#endif
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void eval();
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void step();
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void reset();
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void attach_core();
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void attach_ram(RAM *ram);
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};
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123
hw/unittest/mem_streamer/ram.cpp
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123
hw/unittest/mem_streamer/ram.cpp
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@@ -0,0 +1,123 @@
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// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "ram.h"
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#include "memsim.h"
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RAM::RAM() {
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ram_.clear();
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is_rsp_active_ = false;
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is_rsp_stall_ = false;
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}
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bool RAM::check_duplicate_req(req_t req) {
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for(int i = 0; i < ram_.size(); i++) {
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if (ram_[i].addr == req.addr) {
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std::cout<<"RAM: Duplicate entry. Do not insert..."<<std::endl;
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return true;
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}
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}
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return false;
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}
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int RAM::simulate_cycle_delay() {
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std::cout<<"RAM: # entries: "<<ram_.size()<<std::endl;
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int dequeue_index = -1;
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for (int i = 0; i < ram_.size(); i++) {
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if (!is_rsp_stall_) {
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if (ram_[i].cycles_left > 0) {
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ram_[i].cycles_left -= 1;
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}
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}
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std::cout<<"RAM: # cycles left: "<<ram_[i].cycles_left<<std::endl;
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if (ram_[i].cycles_left == 0) {
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dequeue_index = i;
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}
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}
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return dequeue_index;
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}
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void RAM::insert_req(req_t req) {
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if ( !(this->check_duplicate_req(req)) && req.valid && !req.rw) {
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req_t r;
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r.valid = req.valid;
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r.rw = req.rw;
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r.byteen = req.byteen;
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r.addr = req.addr;
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r.data = req.data;
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r.tag = req.tag & 0b11;
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// Store metadata
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r.cycles_left = MEM_LATENCY;
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std::cout<<"RAM: Insert entry... "<<std::endl;
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std::cout<<"Write? : "<<req.rw<<std::endl;
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ram_.push_back(r);
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}
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}
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uint8_t RAM::is_ready() {
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// return generate_rand(0b1000, 0b1111);
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return 0b1111;
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}
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rsp_t RAM::schedule_rsp() {
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rsp_t rsp;
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int dequeue_index = this->simulate_cycle_delay();
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if (!is_rsp_active_) {
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if (dequeue_index != -1) {
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std::cout<<"RAM: Scheduling response... "<<std::endl;
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is_rsp_active_ = true;
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rsp.valid = 1;
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rsp.mask = generate_rand_mask(ram_[dequeue_index].valid);
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rsp.data = generate_rand(0x20000000, 0x30000000);
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rsp.tag = ram_[dequeue_index].tag;
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std::cout<<std::hex;
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std::cout<<"RAM: Response mask: "<<+rsp.mask<<" | Required mask: "<<+ram_[dequeue_index].valid<<std::endl;
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ram_[dequeue_index].rsp_sent_mask = rsp.mask;
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ram_[dequeue_index].valid = ram_[dequeue_index].valid & ~ram_[dequeue_index].rsp_sent_mask;
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if (0 == ram_[dequeue_index].valid) {
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ram_.erase(ram_.begin() + dequeue_index);
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is_rsp_stall_ = false;
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std::cout<<"RAM: Clear entry... "<<std::endl;
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} else {
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is_rsp_stall_ = true;
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std::cout<<"RAM: Stall... "<<std::endl;
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}
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} else {
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rsp.valid = false;
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}
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}
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return rsp;
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}
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// Schedule response for only one cycle
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void RAM::halt_rsp(rsp_t rsp) {
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if (is_rsp_active_ && rsp.valid && rsp.ready) {
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std::cout<<"RAM: Halt response..."<<std::endl;
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is_rsp_active_ = false;
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}
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}
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64
hw/unittest/mem_streamer/ram.h
Normal file
64
hw/unittest/mem_streamer/ram.h
Normal file
@@ -0,0 +1,64 @@
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// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
|
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// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
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#pragma once
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#include <iostream>
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#include <vector>
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#define MEM_LATENCY 4
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typedef struct {
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uint8_t valid;
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bool rw;
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uint8_t byteen;
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uint32_t addr;
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uint32_t data;
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uint8_t tag;
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uint8_t ready;
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// Metadata
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uint8_t rsp_sent_mask;
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double cycles_left;
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} req_t;
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typedef struct {
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bool valid;
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uint8_t mask;
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uint32_t data;
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uint8_t tag;
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bool ready;
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} rsp_t;
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class RAM {
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private:
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std::vector<req_t> ram_;
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bool is_rsp_active_;
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bool is_rsp_stall_;
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bool check_duplicate_req(req_t req);
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int simulate_cycle_delay();
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public:
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RAM();
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uint8_t is_ready();
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void insert_req(req_t req);
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rsp_t schedule_rsp();
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void halt_rsp(rsp_t rsp);
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};
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//////////////////////////////////////////////////////
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Block a user