Vortex 2.0 changes:
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
This commit is contained in:
Blaise Tine
1
hw/syn/yosys/.gitignore
vendored
Normal file
1
hw/syn/yosys/.gitignore
vendored
Normal file
@@ -0,0 +1 @@
|
||||
build_*/*
|
||||
@@ -1,20 +1,95 @@
|
||||
PROJECT = Vortex
|
||||
TOP_LEVEL_ENTITY = Vortex
|
||||
SRC_FILE = Vortex.sv
|
||||
RTL_DIR = ../../rtl
|
||||
TOP_LEVEL_ENTITY ?= Vortex
|
||||
PREFIX ?= build
|
||||
NUM_CORES ?= 1
|
||||
XLEN ?= 32
|
||||
|
||||
DEFINES = -DNDEBUG -DSYNTHESIS -DEXT_F_DISABLE -DNUM_CORES=1 -DNUM_THREADS=2 -DNUM_WARPS=2 -DMEM_BLOCK_SIZE=64
|
||||
SCRIPT_DIR = ../../../scripts
|
||||
RTL_DIR = ../../../rtl
|
||||
DPI_DIR = ../../../dpi
|
||||
THIRD_PARTY_DIR = ../../../../third_party
|
||||
|
||||
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache
|
||||
CP = cp -rf
|
||||
RMDIR = rm -rf
|
||||
ECHO = @echo
|
||||
|
||||
BUILD_DIR = $(PREFIX)_$(TOP_LEVEL_ENTITY)
|
||||
BIN_DIR = $(BUILD_DIR)/bin
|
||||
|
||||
# control RTL debug tracing states
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_PIPELINE
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_ICACHE
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_DCACHE
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_MEM
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_BANK
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_MSHR
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_TAG
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_DATA
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_AFU
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_GBAR
|
||||
|
||||
# Control logic analyzer monitors
|
||||
DBG_SCOPE_FLAGS += -DDBG_SCOPE_AFU
|
||||
DBG_SCOPE_FLAGS += -DDBG_SCOPE_ISSUE
|
||||
DBG_SCOPE_FLAGS += -DDBG_SCOPE_FETCH
|
||||
DBG_SCOPE_FLAGS += -DDBG_SCOPE_LSU
|
||||
DBG_SCOPE_FLAGS += -DDBG_SCOPE_MSCHED
|
||||
|
||||
# cluster configuration
|
||||
CONFIGS_1c := -DNUM_CLUSTERS=1 -DNUM_CORES=1
|
||||
CONFIGS_2c := -DNUM_CLUSTERS=1 -DNUM_CORES=2
|
||||
CONFIGS_4c := -DNUM_CLUSTERS=1 -DNUM_CORES=4 -DL2_ENABLE
|
||||
CONFIGS_8c := -DNUM_CLUSTERS=1 -DNUM_CORES=8 -DL2_ENABLE
|
||||
CONFIGS_16c := -DNUM_CLUSTERS=1 -DNUM_CORES=16 -DL2_ENABLE
|
||||
CONFIGS_32c := -DNUM_CLUSTERS=2 -DNUM_CORES=16 -DL2_ENABLE
|
||||
CONFIGS_64c := -DNUM_CLUSTERS=4 -DNUM_CORES=16 -DL2_ENABLE
|
||||
CONFIGS += $(CONFIGS_$(NUM_CORES)c)
|
||||
|
||||
# include paths
|
||||
FPU_INCLUDE = -I$(RTL_DIR)/fpu
|
||||
ifneq (,$(findstring FPU_FPNEW,$(CONFIGS)))
|
||||
FPU_INCLUDE += -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
|
||||
endif
|
||||
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache
|
||||
RTL_INCLUDE += $(FPU_INCLUDE)
|
||||
|
||||
# Debugigng
|
||||
ifdef DEBUG
|
||||
CFLAGS += -DNDEBUG -DSCOPE $(DBG_SCOPE_FLAGS)
|
||||
SCOPE_JSON += $(BUILD_DIR)/scope.json
|
||||
else
|
||||
CFLAGS += -DNDEBUG
|
||||
endif
|
||||
|
||||
# Enable scope analyzer
|
||||
ifdef SCOPE
|
||||
CFLAGS += -DSCOPE
|
||||
endif
|
||||
|
||||
# Enable perf counters
|
||||
ifdef PERF
|
||||
CFLAGS += -DPERF_ENABLE
|
||||
endif
|
||||
|
||||
CFLAGS += -DSYNTHESIS -DYOSYS
|
||||
CFLAGS += -DXLEN_$(XLEN)
|
||||
CFLAGS += $(CONFIGS)
|
||||
CFLAGS += $(RTL_INCLUDE)
|
||||
|
||||
# Build targets
|
||||
all: build
|
||||
all: clean build
|
||||
|
||||
output.v:
|
||||
./sv2v.sh $(DEFINES) $(RTL_INCLUDE) -ooutput.v
|
||||
gen-sources: $(BUILD_DIR)/sources.txt
|
||||
$(BUILD_DIR)/sources.txt:
|
||||
mkdir -p $(BUILD_DIR); cd $(BUILD_DIR); $(SCRIPT_DIR)/gen_sources.sh -P $(CFLAGS) -Csrc -Osources.txt
|
||||
|
||||
build: output.v
|
||||
./synth.sh -t$(TOP_LEVEL_ENTITY) -soutput.v
|
||||
$(BUILD_DIR)/project.v: gen-sources
|
||||
cd $(BUILD_DIR); $(SCRIPT_DIR)/sv2v.sh -t$(TOP_LEVEL_ENTITY) -Isrc -oproject.v
|
||||
|
||||
build: $(BUILD_DIR)/project.v
|
||||
cd $(BUILD_DIR); ../synth.sh -t$(TOP_LEVEL_ENTITY) -sproject.v
|
||||
|
||||
elaborate: $(BUILD_DIR)/project.v
|
||||
cd $(BUILD_DIR); ../synth.sh -t$(TOP_LEVEL_ENTITY) -sproject.v -P="elaborate"
|
||||
|
||||
clean:
|
||||
rm -rf output.v *.ys *.log
|
||||
$(RMDIR) $(BUILD_DIR)
|
||||
|
||||
@@ -1,57 +0,0 @@
|
||||
#!/bin/bash
|
||||
|
||||
# this script uses sv2v and yosys tools to run.
|
||||
# sv2v: https://github.com/zachjs/sv2v
|
||||
# yosys: http://www.clifford.at/yosys/
|
||||
|
||||
# exit when any command fails
|
||||
set -e
|
||||
|
||||
source=""
|
||||
includes=()
|
||||
macro_args=""
|
||||
output_file=out.v
|
||||
|
||||
usage() { echo "$0 usage:" && grep " .)\ #" $0; exit 0; }
|
||||
[ $# -eq 0 ] && usage
|
||||
while getopts "o:I:D:h" arg; do
|
||||
case $arg in
|
||||
s) # source
|
||||
source=${OPTARG}
|
||||
;;
|
||||
o) # output-file
|
||||
output_file=${OPTARG}
|
||||
;;
|
||||
I) # include directory
|
||||
includes+=(${OPTARG})
|
||||
;;
|
||||
D) # macro definition
|
||||
macro_args="$macro_args -D${OPTARG}"
|
||||
;;
|
||||
h | *)
|
||||
usage
|
||||
exit 0
|
||||
;;
|
||||
esac
|
||||
done
|
||||
|
||||
# process include paths
|
||||
inc_args=""
|
||||
for dir in "${includes[@]}"
|
||||
do
|
||||
inc_args="$inc_args -I$dir"
|
||||
done
|
||||
|
||||
# process source files
|
||||
file_args=$source
|
||||
for dir in "${includes[@]}"
|
||||
do
|
||||
for file in $(find $dir -maxdepth 1 -name '*.v' -o -name '*.sv' -type f)
|
||||
do
|
||||
echo "file: $file"
|
||||
file_args="$file_args $file"
|
||||
done
|
||||
done
|
||||
|
||||
# system-verilog to verilog conversion
|
||||
sv2v $macro_args $inc_args $file_args -v -w $output_file
|
||||
@@ -1,5 +1,18 @@
|
||||
#!/bin/bash
|
||||
|
||||
# Copyright © 2019-2023
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
# this script uses sv2v and yosys tools to run.
|
||||
# sv2v: https://github.com/zachjs/sv2v
|
||||
# yosys: http://www.clifford.at/yosys/
|
||||
@@ -12,10 +25,48 @@ top_level=""
|
||||
dir_list=()
|
||||
inc_args=""
|
||||
macro_args=""
|
||||
no_warnings=1
|
||||
process="elaborate,netlist,techmap,verilog"
|
||||
|
||||
declare -a excluded_warnings=("Resizing cell port")
|
||||
|
||||
is_excluded_warning() {
|
||||
local warning_text="$1"
|
||||
for exclusion in "${excluded_warnings[@]}"; do
|
||||
if [[ "$warning_text" == *"$exclusion"* ]]; then
|
||||
return $no_warnings
|
||||
fi
|
||||
done
|
||||
return 1
|
||||
}
|
||||
|
||||
checkErrors()
|
||||
{
|
||||
log_file="$1"
|
||||
if grep -q "Error: " "$log_file"; then
|
||||
echo "Error: found errors during synthesis!"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
count=0
|
||||
while IFS= read -r line; do
|
||||
if [[ "$line" == *"Warning:"* ]]; then
|
||||
warning_text="${line#Warning: }"
|
||||
if ! is_excluded_warning "$warning_text"; then
|
||||
count=$(expr $count + 1)
|
||||
fi
|
||||
fi
|
||||
done < $log_file
|
||||
|
||||
if [ "$count" -ne 0 ]; then
|
||||
echo "Error: found $count unexpected warnings during synthesis!"
|
||||
exit $count
|
||||
fi
|
||||
}
|
||||
|
||||
usage() { echo "$0 usage:" && grep " .)\ #" $0; exit 0; }
|
||||
[ $# -eq 0 ] && usage
|
||||
while getopts "s:t:I:D:h" arg; do
|
||||
while getopts "s:t:I:D:P:Wh" arg; do
|
||||
case $arg in
|
||||
s) # source
|
||||
source=${OPTARG}
|
||||
@@ -30,6 +81,12 @@ while getopts "s:t:I:D:h" arg; do
|
||||
D) # macro definition
|
||||
macro_args="$macro_args -D${OPTARG}"
|
||||
;;
|
||||
P) # process
|
||||
process=${OPTARG}
|
||||
;;
|
||||
W) # allow warnings
|
||||
no_warnings=0
|
||||
;;
|
||||
h | *)
|
||||
usage
|
||||
exit 0
|
||||
@@ -43,23 +100,34 @@ done
|
||||
do
|
||||
for file in $(find $dir -maxdepth 1 -name '*.v' -o -name '*.sv' -type f)
|
||||
do
|
||||
echo "read_verilog $macro_args $inc_args -sv $file"
|
||||
echo "read_verilog -defer -nolatches $macro_args $inc_args -sv $file"
|
||||
done
|
||||
done
|
||||
if [ -n "$source" ]; then
|
||||
echo "read_verilog $macro_args $inc_args -sv $source"
|
||||
echo "read_verilog -defer -nolatches $macro_args $inc_args -sv $source"
|
||||
fi
|
||||
|
||||
# generic synthesis
|
||||
echo "synth -top $top_level"
|
||||
# elaborate
|
||||
if echo "$process" | grep -q "elaborate"; then
|
||||
echo "hierarchy -top $top_level"
|
||||
fi
|
||||
|
||||
# convert to netlist
|
||||
if echo "$process" | grep -q "netlist"; then
|
||||
echo "proc; opt"
|
||||
fi
|
||||
|
||||
# mapping to mycells.lib
|
||||
echo "dfflibmap -liberty mycells.lib"
|
||||
echo "abc -liberty mycells.lib"
|
||||
echo "clean"
|
||||
# convert to gate logic
|
||||
if echo "$process" | grep -q "techmap"; then
|
||||
echo "techmap; opt"
|
||||
fi
|
||||
|
||||
# write synthesized design
|
||||
echo "write_verilog synth.v"
|
||||
if echo "$process" | grep -q "verilog"; then
|
||||
echo "write_verilog synth.v"
|
||||
fi
|
||||
} > synth.ys
|
||||
|
||||
yosys -l yosys.log synth.ys
|
||||
yosys -l yosys.log synth.ys
|
||||
|
||||
checkErrors yosys.log
|
||||
|
||||
Reference in New Issue
Block a user