Vortex 2.0 changes:
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
This commit is contained in:
Blaise Tine
@@ -1,141 +1,58 @@
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// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_platform.vh"
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`TRACING_OFF
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module VX_shift_register_nr #(
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parameter DATAW = 1,
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parameter DEPTH = 1,
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parameter NTAPS = 1,
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parameter DEPTHW = $clog2(DEPTH),
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parameter [(DEPTHW*NTAPS)-1:0] TAPS = {NTAPS{DEPTHW'(DEPTH-1)}}
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) (
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input wire clk,
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input wire enable,
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input wire [DATAW-1:0] data_in,
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output wire [(NTAPS*DATAW)-1:0] data_out
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);
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reg [DEPTH-1:0][DATAW-1:0] entries;
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always @(posedge clk) begin
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if (enable) begin
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for (integer i = DEPTH-1; i > 0; --i)
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entries[i] <= entries[i-1];
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entries[0] <= data_in;
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end
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end
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for (genvar i = 0; i < NTAPS; ++i) begin
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assign data_out [i*DATAW+:DATAW] = entries [TAPS[i*DEPTHW+:DEPTHW]];
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end
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endmodule
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module VX_shift_register_wr #(
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parameter DATAW = 1,
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parameter DEPTH = 1,
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parameter NTAPS = 1,
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parameter DEPTHW = $clog2(DEPTH),
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parameter [(DEPTHW*NTAPS)-1:0] TAPS = {NTAPS{DEPTHW'(DEPTH-1)}}
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) (
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input wire clk,
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input wire reset,
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input wire enable,
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input wire [DATAW-1:0] data_in,
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output wire [(NTAPS*DATAW)-1:0] data_out
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);
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reg [DEPTH-1:0][DATAW-1:0] entries;
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always @(posedge clk) begin
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if (reset) begin
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entries <= '0;
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end else if (enable) begin
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for (integer i = DEPTH-1; i > 0; --i)
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entries[i] <= entries[i-1];
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entries[0] <= data_in;
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end
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end
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for (genvar i = 0; i < NTAPS; ++i) begin
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assign data_out [i*DATAW+:DATAW] = entries [TAPS[i*DEPTHW+:DEPTHW]];
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end
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endmodule
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module VX_shift_register #(
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parameter DATAW = 1,
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parameter RESETW = 0,
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parameter DEPTH = 1,
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parameter NTAPS = 1,
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parameter DEPTHW = $clog2(DEPTH),
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parameter [(DEPTHW*NTAPS)-1:0] TAPS = {NTAPS{DEPTHW'(DEPTH-1)}}
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parameter DATAW = 1,
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parameter RESETW = 0,
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parameter DEPTH = 1,
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parameter NUM_TAPS = 1,
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parameter TAP_START = 0,
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parameter TAP_STRIDE = 1
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) (
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input wire clk,
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input wire reset,
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input wire enable,
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input wire [DATAW-1:0] data_in,
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output wire [(NTAPS*DATAW)-1:0] data_out
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input wire clk,
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input wire reset,
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input wire enable,
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input wire [DATAW-1:0] data_in,
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output wire [NUM_TAPS-1:0][DATAW-1:0] data_out
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);
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if (RESETW != 0) begin
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if (RESETW == DATAW) begin
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VX_shift_register_wr #(
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.DATAW (DATAW),
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.DEPTH (DEPTH),
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.NTAPS (NTAPS),
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.TAPS (TAPS)
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) sr (
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.clk (clk),
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.reset (reset),
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.enable (enable),
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.data_in (data_in),
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.data_out (data_out)
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);
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end else begin
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VX_shift_register_wr #(
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.DATAW (RESETW),
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.DEPTH (DEPTH),
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.NTAPS (NTAPS),
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.TAPS (TAPS)
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) sr_wr (
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.clk (clk),
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.reset (reset),
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.enable (enable),
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.data_in (data_in[DATAW-1:DATAW-RESETW]),
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.data_out (data_out[DATAW-1:DATAW-RESETW])
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);
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VX_shift_register_nr #(
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.DATAW (DATAW-RESETW),
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.DEPTH (DEPTH),
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.NTAPS (NTAPS),
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.TAPS (TAPS)
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) sr_nr (
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.clk (clk),
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.enable (enable),
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.data_in (data_in[DATAW-RESETW-1:0]),
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.data_out (data_out[DATAW-RESETW-1:0])
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);
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if (DEPTH != 0) begin
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reg [DEPTH-1:0][DATAW-1:0] entries;
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always @(posedge clk) begin
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for (integer i = 0; i < DATAW; ++i) begin
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if ((i >= (DATAW-RESETW)) && reset) begin
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for (integer j = 0; j < DEPTH; ++j)
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entries[j][i] <= 0;
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end else if (enable) begin
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for (integer j = 1; j < DEPTH; ++j)
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entries[j-1][i] <= entries[j][i];
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entries[DEPTH-1][i] <= data_in[i];
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end
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end
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end
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end else begin
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for (genvar i = 0; i < NUM_TAPS; ++i) begin
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assign data_out[i] = entries[i * TAP_STRIDE + TAP_START];
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end
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end else begin
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`UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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VX_shift_register_nr #(
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.DATAW (DATAW),
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.DEPTH (DEPTH),
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.NTAPS (NTAPS),
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.TAPS (TAPS)
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) sr (
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.clk (clk),
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.enable (enable),
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.data_in (data_in),
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.data_out (data_out)
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);
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end
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`UNUSED_VAR (enable)
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assign data_out = data_in;
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end
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endmodule
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`TRACING_ON
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`TRACING_ON
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