Vortex 2.0 changes:

+ Microarchitecture optimizations
+ 64-bit support
+ Xilinx FPGA support
+ LLVM-16 support
+ Refactoring and quality control fixes

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cleanup

cleanup

cache bindings and memory perf refactory

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hw unit tests fixes

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minor udpate

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hw/rtl/interfaces/VX_warp_ctl_if.sv

@@ -1,35 +1,46 @@
-`ifndef VX_WARP_CTL_IF
-`define VX_WARP_CTL_IF
+// Copyright © 2019-2023
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+// http://www.apache.org/licenses/LICENSE-2.0
+// 
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
 
 `include "VX_define.vh"
 
-interface VX_warp_ctl_if ();
+interface VX_warp_ctl_if import VX_gpu_pkg::*; ();
 
-    wire                    valid;
-    wire [`NW_BITS-1:0]     wid;
-    gpu_types::gpu_tmc_t    tmc;
-    gpu_types::gpu_wspawn_t wspawn;
-    gpu_types::gpu_barrier_t barrier;
-    gpu_types::gpu_split_t  split;
+    wire        valid;
+    wire [`NW_WIDTH-1:0] wid;
+    tmc_t       tmc;
+    wspawn_t    wspawn;
+    split_t     split;
+    join_t      sjoin;
+    barrier_t   barrier;
 
     modport master (
         output valid,
         output wid,
-        output tmc,
         output wspawn,
-        output barrier,
-        output split
+        output tmc,
+        output split,
+        output sjoin,
+        output barrier
     );
 
     modport slave (
         input valid,
         input wid,
-        input tmc,
         input wspawn,
-        input barrier,
-        input split
+        input tmc,
+        input split,
+        input sjoin,
+        input barrier
     );
 
 endinterface
-
-`endif