Vortex 2.0 changes:
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
This commit is contained in:
Blaise Tine
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// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_define.vh"
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module Vortex_axi #(
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parameter AXI_DATA_WIDTH = `VX_MEM_DATA_WIDTH,
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parameter AXI_ADDR_WIDTH = 32,
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parameter AXI_TID_WIDTH = `VX_MEM_TAG_WIDTH,
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parameter AXI_STROBE_WIDTH = (`VX_MEM_DATA_WIDTH / 8)
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module Vortex_axi import VX_gpu_pkg::*; #(
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parameter AXI_DATA_WIDTH = `VX_MEM_DATA_WIDTH,
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parameter AXI_ADDR_WIDTH = `XLEN,
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parameter AXI_TID_WIDTH = `VX_MEM_TAG_WIDTH,
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parameter AXI_NUM_BANKS = 1
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)(
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`SCOPE_IO_DECL
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// Clock
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input wire clk,
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input wire reset,
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// AXI write request address channel
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output wire [AXI_TID_WIDTH-1:0] m_axi_awid,
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output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
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output wire [7:0] m_axi_awlen,
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output wire [2:0] m_axi_awsize,
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output wire [1:0] m_axi_awburst,
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output wire m_axi_awlock,
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output wire [3:0] m_axi_awcache,
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output wire [2:0] m_axi_awprot,
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output wire [3:0] m_axi_awqos,
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output wire m_axi_awvalid,
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input wire m_axi_awready,
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output wire m_axi_awvalid [AXI_NUM_BANKS],
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input wire m_axi_awready [AXI_NUM_BANKS],
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output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr [AXI_NUM_BANKS],
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output wire [AXI_TID_WIDTH-1:0] m_axi_awid [AXI_NUM_BANKS],
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output wire [7:0] m_axi_awlen [AXI_NUM_BANKS],
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output wire [2:0] m_axi_awsize [AXI_NUM_BANKS],
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output wire [1:0] m_axi_awburst [AXI_NUM_BANKS],
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output wire [1:0] m_axi_awlock [AXI_NUM_BANKS],
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output wire [3:0] m_axi_awcache [AXI_NUM_BANKS],
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output wire [2:0] m_axi_awprot [AXI_NUM_BANKS],
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output wire [3:0] m_axi_awqos [AXI_NUM_BANKS],
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output wire [3:0] m_axi_awregion [AXI_NUM_BANKS],
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// AXI write request data channel
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output wire [AXI_DATA_WIDTH-1:0] m_axi_wdata,
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output wire [AXI_STROBE_WIDTH-1:0] m_axi_wstrb,
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output wire m_axi_wlast,
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output wire m_axi_wvalid,
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input wire m_axi_wready,
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output wire m_axi_wvalid [AXI_NUM_BANKS],
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input wire m_axi_wready [AXI_NUM_BANKS],
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output wire [AXI_DATA_WIDTH-1:0] m_axi_wdata [AXI_NUM_BANKS],
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output wire [AXI_DATA_WIDTH/8-1:0] m_axi_wstrb [AXI_NUM_BANKS],
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output wire m_axi_wlast [AXI_NUM_BANKS],
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// AXI write response channel
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input wire [AXI_TID_WIDTH-1:0] m_axi_bid,
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input wire [1:0] m_axi_bresp,
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input wire m_axi_bvalid,
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output wire m_axi_bready,
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input wire m_axi_bvalid [AXI_NUM_BANKS],
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output wire m_axi_bready [AXI_NUM_BANKS],
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input wire [AXI_TID_WIDTH-1:0] m_axi_bid [AXI_NUM_BANKS],
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input wire [1:0] m_axi_bresp [AXI_NUM_BANKS],
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// AXI read request channel
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output wire [AXI_TID_WIDTH-1:0] m_axi_arid,
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output wire [AXI_ADDR_WIDTH-1:0] m_axi_araddr,
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output wire [7:0] m_axi_arlen,
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output wire [2:0] m_axi_arsize,
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output wire [1:0] m_axi_arburst,
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output wire m_axi_arlock,
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output wire [3:0] m_axi_arcache,
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output wire [2:0] m_axi_arprot,
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output wire [3:0] m_axi_arqos,
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output wire m_axi_arvalid,
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input wire m_axi_arready,
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output wire m_axi_arvalid [AXI_NUM_BANKS],
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input wire m_axi_arready [AXI_NUM_BANKS],
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output wire [AXI_ADDR_WIDTH-1:0] m_axi_araddr [AXI_NUM_BANKS],
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output wire [AXI_TID_WIDTH-1:0] m_axi_arid [AXI_NUM_BANKS],
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output wire [7:0] m_axi_arlen [AXI_NUM_BANKS],
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output wire [2:0] m_axi_arsize [AXI_NUM_BANKS],
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output wire [1:0] m_axi_arburst [AXI_NUM_BANKS],
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output wire [1:0] m_axi_arlock [AXI_NUM_BANKS],
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output wire [3:0] m_axi_arcache [AXI_NUM_BANKS],
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output wire [2:0] m_axi_arprot [AXI_NUM_BANKS],
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output wire [3:0] m_axi_arqos [AXI_NUM_BANKS],
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output wire [3:0] m_axi_arregion [AXI_NUM_BANKS],
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// AXI read response channel
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input wire [AXI_TID_WIDTH-1:0] m_axi_rid,
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input wire [AXI_DATA_WIDTH-1:0] m_axi_rdata,
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input wire [1:0] m_axi_rresp,
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input wire m_axi_rlast,
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input wire m_axi_rvalid,
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output wire m_axi_rready,
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input wire m_axi_rvalid [AXI_NUM_BANKS],
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output wire m_axi_rready [AXI_NUM_BANKS],
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input wire [AXI_DATA_WIDTH-1:0] m_axi_rdata [AXI_NUM_BANKS],
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input wire m_axi_rlast [AXI_NUM_BANKS],
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input wire [AXI_TID_WIDTH-1:0] m_axi_rid [AXI_NUM_BANKS],
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input wire [1:0] m_axi_rresp [AXI_NUM_BANKS],
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// DCR write request
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input wire dcr_wr_valid,
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input wire [`VX_DCR_ADDR_WIDTH-1:0] dcr_wr_addr,
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input wire [`VX_DCR_DATA_WIDTH-1:0] dcr_wr_data,
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// Status
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output wire busy
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);
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`STATIC_ASSERT((AXI_DATA_WIDTH == `VX_MEM_DATA_WIDTH), ("invalid memory data size: current=%0d, expected=%0d", AXI_DATA_WIDTH, `VX_MEM_DATA_WIDTH))
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`STATIC_ASSERT((AXI_ADDR_WIDTH >= `XLEN), ("invalid memory address size: current=%0d, expected=%0d", AXI_ADDR_WIDTH, `VX_MEM_ADDR_WIDTH))
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//`STATIC_ASSERT((AXI_TID_WIDTH >= `VX_MEM_TAG_WIDTH), ("invalid memory tag size: current=%0d, expected=%0d", AXI_TID_WIDTH, `VX_MEM_TAG_WIDTH))
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wire mem_req_valid;
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wire mem_req_rw;
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wire [`VX_MEM_BYTEEN_WIDTH-1:0] mem_req_byteen;
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@@ -72,16 +98,33 @@ module Vortex_axi #(
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wire [`VX_MEM_DATA_WIDTH-1:0] mem_rsp_data;
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wire [`VX_MEM_TAG_WIDTH-1:0] mem_rsp_tag;
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wire mem_rsp_ready;
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wire [`XLEN-1:0] m_axi_awaddr_unqual [AXI_NUM_BANKS];
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wire [`XLEN-1:0] m_axi_araddr_unqual [AXI_NUM_BANKS];
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wire [`VX_MEM_TAG_WIDTH-1:0] m_axi_awid_unqual [AXI_NUM_BANKS];
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wire [`VX_MEM_TAG_WIDTH-1:0] m_axi_arid_unqual [AXI_NUM_BANKS];
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wire [`VX_MEM_TAG_WIDTH-1:0] m_axi_bid_unqual [AXI_NUM_BANKS];
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wire [`VX_MEM_TAG_WIDTH-1:0] m_axi_rid_unqual [AXI_NUM_BANKS];
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for (genvar i = 0; i < AXI_NUM_BANKS; ++i) begin
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assign m_axi_awaddr[i] = `XLEN'(m_axi_awaddr_unqual[i]);
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assign m_axi_araddr[i] = `XLEN'(m_axi_araddr_unqual[i]);
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assign m_axi_awid[i] = AXI_TID_WIDTH'(m_axi_awid_unqual[i]);
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assign m_axi_arid[i] = AXI_TID_WIDTH'(m_axi_arid_unqual[i]);
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assign m_axi_rid_unqual[i] = `VX_MEM_TAG_WIDTH'(m_axi_rid[i]);
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assign m_axi_bid_unqual[i] = `VX_MEM_TAG_WIDTH'(m_axi_bid[i]);
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end
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VX_axi_adapter #(
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.VX_DATA_WIDTH (`VX_MEM_DATA_WIDTH),
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.VX_ADDR_WIDTH (`VX_MEM_ADDR_WIDTH),
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.VX_TAG_WIDTH (`VX_MEM_TAG_WIDTH),
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.VX_BYTEEN_WIDTH (AXI_STROBE_WIDTH),
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.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
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.AXI_ADDR_WIDTH (AXI_ADDR_WIDTH),
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.AXI_TID_WIDTH (AXI_TID_WIDTH),
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.AXI_STROBE_WIDTH (AXI_STROBE_WIDTH)
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.DATA_WIDTH (`VX_MEM_DATA_WIDTH),
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.ADDR_WIDTH (`XLEN),
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.TAG_WIDTH (`VX_MEM_TAG_WIDTH),
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.NUM_BANKS (AXI_NUM_BANKS),
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.OUT_REG_RSP((AXI_NUM_BANKS > 1) ? 2 : 0)
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) axi_adapter (
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.clk (clk),
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.reset (reset),
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@@ -98,9 +141,11 @@ module Vortex_axi #(
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.mem_rsp_data (mem_rsp_data),
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.mem_rsp_tag (mem_rsp_tag),
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.mem_rsp_ready (mem_rsp_ready),
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.m_axi_awid (m_axi_awid),
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.m_axi_awaddr (m_axi_awaddr),
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.m_axi_awvalid (m_axi_awvalid),
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.m_axi_awready (m_axi_awready),
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.m_axi_awaddr (m_axi_awaddr_unqual),
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.m_axi_awid (m_axi_awid_unqual),
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.m_axi_awlen (m_axi_awlen),
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.m_axi_awsize (m_axi_awsize),
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.m_axi_awburst (m_axi_awburst),
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@@ -108,22 +153,23 @@ module Vortex_axi #(
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.m_axi_awcache (m_axi_awcache),
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.m_axi_awprot (m_axi_awprot),
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.m_axi_awqos (m_axi_awqos),
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.m_axi_awvalid (m_axi_awvalid),
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.m_axi_awready (m_axi_awready),
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.m_axi_awregion (m_axi_awregion),
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.m_axi_wvalid (m_axi_wvalid),
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.m_axi_wready (m_axi_wready),
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.m_axi_wdata (m_axi_wdata),
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.m_axi_wstrb (m_axi_wstrb),
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.m_axi_wlast (m_axi_wlast),
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.m_axi_wvalid (m_axi_wvalid),
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.m_axi_wready (m_axi_wready),
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.m_axi_bid (m_axi_bid),
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.m_axi_bresp (m_axi_bresp),
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.m_axi_bvalid (m_axi_bvalid),
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.m_axi_bready (m_axi_bready),
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.m_axi_bid (m_axi_bid_unqual),
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.m_axi_bresp (m_axi_bresp),
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.m_axi_arid (m_axi_arid),
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.m_axi_araddr (m_axi_araddr),
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.m_axi_arvalid (m_axi_arvalid),
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.m_axi_arready (m_axi_arready),
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.m_axi_araddr (m_axi_araddr_unqual),
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.m_axi_arid (m_axi_arid_unqual),
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.m_axi_arlen (m_axi_arlen),
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.m_axi_arsize (m_axi_arsize),
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.m_axi_arburst (m_axi_arburst),
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@@ -131,18 +177,21 @@ module Vortex_axi #(
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.m_axi_arcache (m_axi_arcache),
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.m_axi_arprot (m_axi_arprot),
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.m_axi_arqos (m_axi_arqos),
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.m_axi_arvalid (m_axi_arvalid),
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.m_axi_arready (m_axi_arready),
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.m_axi_arregion (m_axi_arregion),
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.m_axi_rid (m_axi_rid),
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.m_axi_rdata (m_axi_rdata),
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.m_axi_rresp (m_axi_rresp),
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.m_axi_rlast (m_axi_rlast),
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.m_axi_rvalid (m_axi_rvalid),
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.m_axi_rready (m_axi_rready)
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.m_axi_rready (m_axi_rready),
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.m_axi_rdata (m_axi_rdata),
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.m_axi_rlast (m_axi_rlast) ,
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.m_axi_rid (m_axi_rid_unqual),
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.m_axi_rresp (m_axi_rresp)
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);
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`SCOPE_IO_SWITCH (1)
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Vortex vortex (
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`SCOPE_IO_BIND (0)
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.clk (clk),
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.reset (reset),
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@@ -159,7 +208,11 @@ module Vortex_axi #(
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.mem_rsp_tag (mem_rsp_tag),
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.mem_rsp_ready (mem_rsp_ready),
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.dcr_wr_valid (dcr_wr_valid),
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.dcr_wr_addr (dcr_wr_addr),
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.dcr_wr_data (dcr_wr_data),
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.busy (busy)
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);
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endmodule
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endmodule
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