Vortex 2.0 changes:
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
This commit is contained in:
Blaise Tine
@@ -1,195 +1,172 @@
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// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_define.vh"
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module VX_cluster #(
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module VX_cluster import VX_gpu_pkg::*; #(
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parameter CLUSTER_ID = 0
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) (
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`SCOPE_IO_VX_cluster
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`SCOPE_IO_DECL
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// Clock
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input wire clk,
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input wire reset,
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input wire clk,
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input wire reset,
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// Memory request
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output wire mem_req_valid,
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output wire mem_req_rw,
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output wire [`L2_MEM_BYTEEN_WIDTH-1:0] mem_req_byteen,
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output wire [`L2_MEM_ADDR_WIDTH-1:0] mem_req_addr,
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output wire [`L2_MEM_DATA_WIDTH-1:0] mem_req_data,
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output wire [`L2_MEM_TAG_WIDTH-1:0] mem_req_tag,
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input wire mem_req_ready,
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`ifdef PERF_ENABLE
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VX_mem_perf_if.slave mem_perf_if,
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`endif
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// Memory response
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input wire mem_rsp_valid,
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input wire [`L2_MEM_DATA_WIDTH-1:0] mem_rsp_data,
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input wire [`L2_MEM_TAG_WIDTH-1:0] mem_rsp_tag,
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output wire mem_rsp_ready,
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// DCRs
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VX_dcr_bus_if.slave dcr_bus_if,
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// Memory
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VX_mem_bus_if.master mem_bus_if,
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// simulation helper signals
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output wire sim_ebreak,
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output wire [`NUM_REGS-1:0][`XLEN-1:0] sim_wb_value,
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// Status
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output wire busy
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);
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`STATIC_ASSERT((`L2_ENABLE == 0 || `NUM_CORES > 1), ("invalid parameter"))
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output wire busy
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);
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wire [`NUM_CORES-1:0] per_core_mem_req_valid;
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wire [`NUM_CORES-1:0] per_core_mem_req_rw;
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wire [`NUM_CORES-1:0][`DCACHE_MEM_BYTEEN_WIDTH-1:0] per_core_mem_req_byteen;
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wire [`NUM_CORES-1:0][`DCACHE_MEM_ADDR_WIDTH-1:0] per_core_mem_req_addr;
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wire [`NUM_CORES-1:0][`DCACHE_MEM_DATA_WIDTH-1:0] per_core_mem_req_data;
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wire [`NUM_CORES-1:0][`L1_MEM_TAG_WIDTH-1:0] per_core_mem_req_tag;
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wire [`NUM_CORES-1:0] per_core_mem_req_ready;
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`ifdef SCOPE
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localparam scope_socket = 0;
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`SCOPE_IO_SWITCH (scope_socket + `NUM_SOCKETS);
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`endif
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wire [`NUM_CORES-1:0] per_core_mem_rsp_valid;
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wire [`NUM_CORES-1:0][`DCACHE_MEM_DATA_WIDTH-1:0] per_core_mem_rsp_data;
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wire [`NUM_CORES-1:0][`L1_MEM_TAG_WIDTH-1:0] per_core_mem_rsp_tag;
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wire [`NUM_CORES-1:0] per_core_mem_rsp_ready;
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`ifdef GBAR_ENABLE
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wire [`NUM_CORES-1:0] per_core_busy;
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VX_gbar_bus_if per_socket_gbar_bus_if[`NUM_SOCKETS]();
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VX_gbar_bus_if gbar_bus_if();
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for (genvar i = 0; i < `NUM_CORES; i++) begin
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`RESET_RELAY (gbar_reset, reset);
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`RESET_RELAY (core_reset);
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VX_gbar_arb #(
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.NUM_REQS (`NUM_SOCKETS),
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.OUT_REG ((`NUM_SOCKETS > 2) ? 1 : 0) // bgar_unit has no backpressure
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) gbar_arb (
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.clk (clk),
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.reset (gbar_reset),
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.bus_in_if (per_socket_gbar_bus_if),
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.bus_out_if (gbar_bus_if)
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);
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VX_core #(
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.CORE_ID(i + (CLUSTER_ID * `NUM_CORES))
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) core (
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`SCOPE_BIND_VX_cluster_core(i)
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VX_gbar_unit #(
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.INSTANCE_ID ($sformatf("gbar%0d", CLUSTER_ID))
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) gbar_unit (
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.clk (clk),
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.reset (gbar_reset),
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.gbar_bus_if (gbar_bus_if)
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);
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`endif
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.clk (clk),
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.reset (core_reset),
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.mem_req_valid (per_core_mem_req_valid[i]),
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.mem_req_rw (per_core_mem_req_rw [i]),
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.mem_req_byteen (per_core_mem_req_byteen[i]),
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.mem_req_addr (per_core_mem_req_addr [i]),
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.mem_req_data (per_core_mem_req_data [i]),
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.mem_req_tag (per_core_mem_req_tag [i]),
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.mem_req_ready (per_core_mem_req_ready[i]),
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.mem_rsp_valid (per_core_mem_rsp_valid[i]),
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.mem_rsp_data (per_core_mem_rsp_data [i]),
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.mem_rsp_tag (per_core_mem_rsp_tag [i]),
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.mem_rsp_ready (per_core_mem_rsp_ready[i]),
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.busy (per_core_busy [i])
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);
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end
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`ifdef PERF_ENABLE
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VX_mem_perf_if mem_perf_tmp_if();
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cache_perf_t perf_l2cache;
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assign busy = (| per_core_busy);
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assign mem_perf_tmp_if.icache = 'x;
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assign mem_perf_tmp_if.dcache = 'x;
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assign mem_perf_tmp_if.l2cache = perf_l2cache;
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assign mem_perf_tmp_if.l3cache = mem_perf_if.l3cache;
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assign mem_perf_tmp_if.smem = 'x;
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assign mem_perf_tmp_if.mem = mem_perf_if.mem;
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`endif
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if (`L2_ENABLE) begin
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VX_mem_bus_if #(
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.DATA_SIZE (`L1_LINE_SIZE),
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.TAG_WIDTH (L1_MEM_ARB_TAG_WIDTH)
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) per_socket_mem_bus_if[`NUM_SOCKETS]();
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`RESET_RELAY (l2_reset, reset);
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VX_cache_wrap #(
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.INSTANCE_ID ("l2cache"),
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.CACHE_SIZE (`L2_CACHE_SIZE),
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.LINE_SIZE (`L2_LINE_SIZE),
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.NUM_BANKS (`L2_NUM_BANKS),
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.NUM_WAYS (`L2_NUM_WAYS),
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.WORD_SIZE (L2_WORD_SIZE),
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.NUM_REQS (L2_NUM_REQS),
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.CRSQ_SIZE (`L2_CRSQ_SIZE),
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.MSHR_SIZE (`L2_MSHR_SIZE),
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.MRSQ_SIZE (`L2_MRSQ_SIZE),
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.MREQ_SIZE (`L2_MREQ_SIZE),
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.TAG_WIDTH (L1_MEM_ARB_TAG_WIDTH),
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.WRITE_ENABLE (1),
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.UUID_WIDTH (`UUID_WIDTH),
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.CORE_OUT_REG (2),
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.MEM_OUT_REG (2),
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.NC_ENABLE (1),
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.PASSTHRU (!`L2_ENABLED)
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) l2cache (
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.clk (clk),
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.reset (l2_reset),
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`ifdef PERF_ENABLE
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VX_perf_cache_if perf_l2cache_if();
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.cache_perf (perf_l2cache),
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`endif
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.core_bus_if (per_socket_mem_bus_if),
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.mem_bus_if (mem_bus_if)
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);
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`RESET_RELAY (l2_reset);
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///////////////////////////////////////////////////////////////////////////
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VX_cache #(
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.CACHE_ID (`L2_CACHE_ID),
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.CACHE_SIZE (`L2_CACHE_SIZE),
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.CACHE_LINE_SIZE (`L2_CACHE_LINE_SIZE),
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.NUM_BANKS (`L2_NUM_BANKS),
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.NUM_PORTS (`L2_NUM_PORTS),
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.WORD_SIZE (`L2_WORD_SIZE),
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.NUM_REQS (`L2_NUM_REQS),
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.CREQ_SIZE (`L2_CREQ_SIZE),
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.CRSQ_SIZE (`L2_CRSQ_SIZE),
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.MSHR_SIZE (`L2_MSHR_SIZE),
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.MRSQ_SIZE (`L2_MRSQ_SIZE),
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.MREQ_SIZE (`L2_MREQ_SIZE),
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.WRITE_ENABLE (1),
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.CORE_TAG_WIDTH (`L1_MEM_TAG_WIDTH),
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.CORE_TAG_ID_BITS (0),
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.MEM_TAG_WIDTH (`L2_MEM_TAG_WIDTH),
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.NC_ENABLE (1)
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) l2cache (
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`SCOPE_BIND_VX_cluster_l2cache
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.clk (clk),
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.reset (l2_reset),
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wire [`NUM_SOCKETS-1:0] per_socket_sim_ebreak;
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wire [`NUM_SOCKETS-1:0][`NUM_REGS-1:0][`XLEN-1:0] per_socket_sim_wb_value;
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assign sim_ebreak = per_socket_sim_ebreak[0];
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assign sim_wb_value = per_socket_sim_wb_value[0];
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`UNUSED_VAR (per_socket_sim_ebreak)
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`UNUSED_VAR (per_socket_sim_wb_value)
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VX_dcr_bus_if socket_dcr_bus_tmp_if();
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assign socket_dcr_bus_tmp_if.write_valid = dcr_bus_if.write_valid && (dcr_bus_if.write_addr >= `VX_DCR_BASE_STATE_BEGIN && dcr_bus_if.write_addr < `VX_DCR_BASE_STATE_END);
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assign socket_dcr_bus_tmp_if.write_addr = dcr_bus_if.write_addr;
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assign socket_dcr_bus_tmp_if.write_data = dcr_bus_if.write_data;
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wire [`NUM_SOCKETS-1:0] per_socket_busy;
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`BUFFER_DCR_BUS_IF (socket_dcr_bus_if, socket_dcr_bus_tmp_if, (`NUM_SOCKETS > 1));
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// Generate all sockets
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for (genvar i = 0; i < `NUM_SOCKETS; ++i) begin
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`RESET_RELAY (socket_reset, reset);
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VX_socket #(
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.SOCKET_ID ((CLUSTER_ID * `NUM_SOCKETS) + i)
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) socket (
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`SCOPE_IO_BIND (scope_socket+i)
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.clk (clk),
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.reset (socket_reset),
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`ifdef PERF_ENABLE
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.perf_cache_if (perf_l2cache_if),
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.mem_perf_if (mem_perf_tmp_if),
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`endif
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.dcr_bus_if (socket_dcr_bus_if),
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.mem_bus_if (per_socket_mem_bus_if[i]),
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`ifdef GBAR_ENABLE
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.gbar_bus_if (per_socket_gbar_bus_if[i]),
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`endif
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// Core request
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.core_req_valid (per_core_mem_req_valid),
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.core_req_rw (per_core_mem_req_rw),
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.core_req_byteen (per_core_mem_req_byteen),
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.core_req_addr (per_core_mem_req_addr),
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.core_req_data (per_core_mem_req_data),
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.core_req_tag (per_core_mem_req_tag),
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.core_req_ready (per_core_mem_req_ready),
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// Core response
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.core_rsp_valid (per_core_mem_rsp_valid),
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.core_rsp_data (per_core_mem_rsp_data),
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.core_rsp_tag (per_core_mem_rsp_tag),
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.core_rsp_ready (per_core_mem_rsp_ready),
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`UNUSED_PIN (core_rsp_tmask),
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// Memory request
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.mem_req_valid (mem_req_valid),
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.mem_req_rw (mem_req_rw),
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.mem_req_byteen (mem_req_byteen),
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.mem_req_addr (mem_req_addr),
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.mem_req_data (mem_req_data),
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.mem_req_tag (mem_req_tag),
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.mem_req_ready (mem_req_ready),
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// Memory response
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.mem_rsp_valid (mem_rsp_valid),
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.mem_rsp_tag (mem_rsp_tag),
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.mem_rsp_data (mem_rsp_data),
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.mem_rsp_ready (mem_rsp_ready)
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.sim_ebreak (per_socket_sim_ebreak[i]),
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.sim_wb_value (per_socket_sim_wb_value[i]),
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.busy (per_socket_busy[i])
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);
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end else begin
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`RESET_RELAY (mem_arb_reset);
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VX_mem_arb #(
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.NUM_REQS (`NUM_CORES),
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.DATA_WIDTH (`DCACHE_MEM_DATA_WIDTH),
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.ADDR_WIDTH (`DCACHE_MEM_ADDR_WIDTH),
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.TAG_IN_WIDTH (`L1_MEM_TAG_WIDTH),
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.TYPE ("R"),
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.TAG_SEL_IDX (1), // Skip 0 for NC flag
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.BUFFERED_REQ (1),
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.BUFFERED_RSP (1)
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) mem_arb (
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.clk (clk),
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.reset (mem_arb_reset),
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// Core request
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.req_valid_in (per_core_mem_req_valid),
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.req_rw_in (per_core_mem_req_rw),
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.req_byteen_in (per_core_mem_req_byteen),
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.req_addr_in (per_core_mem_req_addr),
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.req_data_in (per_core_mem_req_data),
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.req_tag_in (per_core_mem_req_tag),
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.req_ready_in (per_core_mem_req_ready),
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// Memory request
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.req_valid_out (mem_req_valid),
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.req_rw_out (mem_req_rw),
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.req_byteen_out (mem_req_byteen),
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.req_addr_out (mem_req_addr),
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.req_data_out (mem_req_data),
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.req_tag_out (mem_req_tag),
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.req_ready_out (mem_req_ready),
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// Core response
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.rsp_valid_out (per_core_mem_rsp_valid),
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.rsp_data_out (per_core_mem_rsp_data),
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.rsp_tag_out (per_core_mem_rsp_tag),
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.rsp_ready_out (per_core_mem_rsp_ready),
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// Memory response
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.rsp_valid_in (mem_rsp_valid),
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.rsp_tag_in (mem_rsp_tag),
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.rsp_data_in (mem_rsp_data),
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.rsp_ready_in (mem_rsp_ready)
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);
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end
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`BUFFER_BUSY (busy, (| per_socket_busy), (`NUM_SOCKETS > 1));
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endmodule
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