From c0fdee5787dab3be3ee1acf82d4c0372d3e78089 Mon Sep 17 00:00:00 2001
From: Krishna Yalamarthy <kyalamarthy6@boson.cc.gt.atl.ga.us>
Date: Sun, 21 Mar 2021 22:55:24 -0400
Subject: [PATCH] bilinear sampling

---
 hw/rtl/tex_unit/VX_bilerp.v      |  71 ++++++++++++++++++
 hw/rtl/tex_unit/VX_lerp.v        |  18 +++++
 hw/rtl/tex_unit/VX_tex_define.vh |   5 +-
 hw/rtl/tex_unit/VX_tex_format.v  | 122 +++++++++++++++++++++----------
 hw/rtl/tex_unit/VX_tex_sampler.v |  80 +++++++++++++-------
 5 files changed, 229 insertions(+), 67 deletions(-)
 create mode 100644 hw/rtl/tex_unit/VX_bilerp.v
 create mode 100644 hw/rtl/tex_unit/VX_lerp.v

diff --git a/hw/rtl/tex_unit/VX_bilerp.v b/hw/rtl/tex_unit/VX_bilerp.v
new file mode 100644
index 00000000..5493bd9a
--- /dev/null
+++ b/hw/rtl/tex_unit/VX_bilerp.v
@@ -0,0 +1,71 @@
+`include "VX_tex_define.vh"
+
+module VX_bilerp #(
+    parameter CORE_ID = 0
+) (
+    input wire [`BLEND_FRAC_64-1:0]   blendU, //blendU
+    input wire [`BLEND_FRAC_64-1:0]   blendV,  //blendV
+
+    input wire [3:0][63:0]            texels,
+    input wire [`TEX_FORMAT_BITS-1:0] color_enable,
+
+    output wire [31:0]                sampled_data
+);  
+    `UNUSED_PARAM (CORE_ID)
+    `UNUSED_VAR(color_enable)
+
+    wire [63:0] UL_lerp;
+    wire [63:0] UH_lerp;
+    wire [63:0] V_lerp;
+    reg [31:0] sampled_r;
+
+    VX_lerp_64 #(
+    ) UL_lerp (
+    .blend(blendU), 
+    .in_texels({texels[1], texels[0]}),
+
+    .lerp_texel(UL_lerp)
+    );  
+
+    VX_lerp_64 #(
+    ) UH_lerp (
+    .blend(blendU), 
+    .in_texels({texels[3], texels[2]}),
+
+    .lerp_texel(UH_lerp)
+    );  
+
+    VX_lerp_64 #(
+    ) V_lerp (
+    .blend(blendV), 
+    .in_texels({UH_lerp, UL_lerp}),
+
+    .lerp_texel(V_lerp)
+    );  
+
+    always @(*) begin
+        if(color_enable[3]==1) //R
+            sampled_r[31:24] = V_lerp[55:48];
+        else
+            sampled_r[31:24] = {`TEX_COLOR_BITS{1'b0}};
+
+        if(color_enable[2]==1) //G
+            sampled_r[23:16] = V_lerp[39:32];
+        else
+            sampled_r[23:16] = {`TEX_COLOR_BITS{1'b0}};
+
+        if(color_enable[1]==1) //B
+            sampled_r[15:8] = V_lerp[23:16];
+        else
+            sampled_r[15:8] = {`TEX_COLOR_BITS{1'b0}};
+
+        if(color_enable[0]==1) //A
+            sampled_r[7:0] = V_lerp[7:0];
+        else
+            sampled_r[7:0] = {`TEX_COLOR_BITS{1'b1}};
+    end
+
+
+    assign sampled_data = sampled_r;
+
+endmodule
\ No newline at end of file
diff --git a/hw/rtl/tex_unit/VX_lerp.v b/hw/rtl/tex_unit/VX_lerp.v
new file mode 100644
index 00000000..40e0baf8
--- /dev/null
+++ b/hw/rtl/tex_unit/VX_lerp.v
@@ -0,0 +1,18 @@
+`include "VX_tex_define.vh"
+
+module VX_lerp_64 #(
+) (
+    input wire [`BLEND_FRAC_64-1:0]   blend, 
+    input wire [1:0][63:0]            in_texels,
+
+    output wire [63:0]                lerp_texel
+);  
+
+    wire [63:0] lerp_i1;
+    wire [63:0] lerp_i2; // >> BLEND_FRAC_64 / >> 8
+
+    assign lerp_i1 = (in_texels[0] - in_texels[1]) * blend;
+    assign lerp_i2 = in_texels[1] + {8'h00,lerp_i1[63:56], 8'h00,lerp_i1[47:40], 8'h00,lerp_i1[31:24], 8'h00,lerp_i1[15:8]};
+    assign lerp_texel = lerp_i2 & 64'h00ff00ff00ff00ff;
+
+endmodule
\ No newline at end of file
diff --git a/hw/rtl/tex_unit/VX_tex_define.vh b/hw/rtl/tex_unit/VX_tex_define.vh
index 0286ae65..ef305c76 100644
--- a/hw/rtl/tex_unit/VX_tex_define.vh
+++ b/hw/rtl/tex_unit/VX_tex_define.vh
@@ -11,6 +11,9 @@
 
 `define CLAMP(x,lo,hi)  ((x < lo) ? lo : ((x > hi) ? hi : x))
 
+`define BLEND_FRAC_64    8
+`define LERP_64(x1,x2,frac) ((x2 + (((x1 - x2) * frac) >> `BLEND_FRAC_64)) & 64'h00ff00ff00ff00ff)
+
 `define TEX_ADDR_BITS    32
 `define TEX_FORMAT_BITS  3
 `define TEX_WRAP_BITS    2
@@ -26,7 +29,7 @@
 `define MAX_COLOR_WIDTH   8
 `define NUM_COLOR_CHANNEL 4  
 
-`define TEX_COLOR_BITS    32
+`define TEX_COLOR_BITS    8
 
 `define R5G6B5            `TEX_FORMAT_BITS'h1
 `define R8G8B8            `TEX_FORMAT_BITS'h2
diff --git a/hw/rtl/tex_unit/VX_tex_format.v b/hw/rtl/tex_unit/VX_tex_format.v
index 9d2ddd7e..6279c6b7 100644
--- a/hw/rtl/tex_unit/VX_tex_format.v
+++ b/hw/rtl/tex_unit/VX_tex_format.v
@@ -1,55 +1,101 @@
 `include "VX_tex_define.vh"
 
 module VX_tex_format #(
-    parameter CORE_ID = 0
+    parameter CORE_ID = 0,
+    parameter NUM_TEXELS = 4 //BILINEAR
 ) (
-    input wire [31:0]                    texel_data,
+    input wire [NUM_TEXELS-1:0][31:0]    texel_data,
     input wire [`TEX_FORMAT_BITS-1:0]    format,
 
     output wire [`NUM_COLOR_CHANNEL-1:0] color_enable,
-    output wire [`TEX_COLOR_BITS-1:0]    R,
-    output wire [`TEX_COLOR_BITS-1:0]    G,
-    output wire [`TEX_COLOR_BITS-1:0]    B,
-    output wire [`TEX_COLOR_BITS-1:0]    A
+    output wire [NUM_TEXELS-1:0][63:0]   formatted_texel     
 );  
     `UNUSED_PARAM (CORE_ID)
 
     reg [`NUM_COLOR_CHANNEL-1:0] color_enable_r;
-    reg [`TEX_COLOR_BITS-1:0]    R_r;
-    reg [`TEX_COLOR_BITS-1:0]    G_r;
-    reg [`TEX_COLOR_BITS-1:0]    B_r;
-    reg [`TEX_COLOR_BITS-1:0]    A_r;
+    reg [NUM_TEXELS][63:0]       formatted_texel_r;    
 
     always @(*) begin
-        case (format)
-            `R5G6B5: begin
-                R_r = `TEX_COLOR_BITS'(texel_data[15:11]);
-                G_r = `TEX_COLOR_BITS'(texel_data[10:5]);
-                B_r = `TEX_COLOR_BITS'(texel_data[4:0]);
-                A_r = {`TEX_COLOR_BITS{1'b0}};
-                color_enable_r = 4'b1110;
-            end
-            `R8G8B8: begin
-                R_r = `TEX_COLOR_BITS'(texel_data[23:16]);
-                G_r = `TEX_COLOR_BITS'(texel_data[15:8]);
-                B_r = `TEX_COLOR_BITS'(texel_data[7:0]);
-                A_r = {`TEX_COLOR_BITS{1'b0}};
-                color_enable_r = 4'b1110;
-            end
-            default: begin // `R8G8B8A8:
-                R_r = `TEX_COLOR_BITS'(texel_data[31:24]);
-                G_r = `TEX_COLOR_BITS'(texel_data[23:16]);
-                B_r = `TEX_COLOR_BITS'(texel_data[15:8]);
-                A_r = `TEX_COLOR_BITS'(texel_data[7:0]);
-                color_enable_r = 4'b1111;
-            end
-        endcase
+        for (integer i = 0; i<NUM_TEXELS ;i++ ) begin
+            case (format)
+                `R5G6B5: begin
+                    formatted_texel_r[i][55:48] = `TEX_COLOR_BITS'(texel_data[i][15:11]);
+                    formatted_texel_r[i][39:32] = `TEX_COLOR_BITS'(texel_data[i][10:5]);
+                    formatted_texel_r[i][23:16] = `TEX_COLOR_BITS'(texel_data[i][4:0]);
+                    formatted_texel_r[i][7:0]   = {`TEX_COLOR_BITS{1'b0}};
+                    if (i == 0)
+                        color_enable_r = 4'b1110;
+                end
+                `R8G8B8: begin
+                    formatted_texel_r[i][55:48] = `TEX_COLOR_BITS'(texel_data[i][23:16]);
+                    formatted_texel_r[i][39:32] = `TEX_COLOR_BITS'(texel_data[i][15:8]);
+                    formatted_texel_r[i][23:16] = `TEX_COLOR_BITS'(texel_data[i][7:0]);
+                    formatted_texel_r[i][7:0]   = {`TEX_COLOR_BITS{1'b0}};
+                    if (i == 0)
+                        color_enable_r = 4'b1110;
+                end
+                default: begin // `R8G8B8A8:
+                    formatted_texel_r[i][55:48] = `TEX_COLOR_BITS'(texel_data[i][31:24]);
+                    formatted_texel_r[i][39:32] = `TEX_COLOR_BITS'(texel_data[i][23:16]);
+                    formatted_texel_r[i][23:16] = `TEX_COLOR_BITS'(texel_data[i][15:8]);
+                    formatted_texel_r[i][7:0]   = `TEX_COLOR_BITS'(texel_data[i][7:0]);
+                    if (i == 0)
+                        color_enable_r = 4'b1111;
+                end
+            endcase
+        end
     end
 
     assign color_enable = color_enable_r;
-    assign R = R_r;
-    assign G = G_r;
-    assign B = B_r;
-    assign A = A_r;   
+    assign formatted_texel = formatted_texel_r & 64'h00ff00ff00ff00ff;
+
+endmodule
+
+// module VX_tex_format #(
+//     parameter CORE_ID = 0
+// ) (
+//     input wire [`TEX_FORMAT_BITS-1:0]   format,
+//     input wire [`NUM_COLOR_CHANNEL-1:0] color_enable,
+
+//     input wire [`TEX_COLOR_BITS-1:0]    R,
+//     input wire [`TEX_COLOR_BITS-1:0]    G,
+//     input wire [`TEX_COLOR_BITS-1:0]    B,
+//     input wire [`TEX_COLOR_BITS-1:0]    A,
+
+//     output wire [31:0]                  texel_sampled
+// );  
+//     `UNUSED_PARAM (CORE_ID)
+//     `UNUSED_VAR(color_enable)
+
+//     reg [63:0]  sampled_r;
+
+//     always @(*) begin
+//         case (format)
+//             `R5G6B5: begin
+//                 sampled_r[31:16] = 'd0;
+//                 sampled_r[15:11] = R[4:0];
+//                 sampled_r[10:5] = G[5:0];
+//                 sampled_r[4:0] = B[4:0];
+//             end
+
+//             `R8G8B8: begin
+//                 sampled_r[31:24] = 'd0;
+//                 sampled_r[23:16] = R;
+//                 sampled_r[15:8]  = G;
+//                 sampled_r[7:0]   = B;
+//             end
+            
+//             default: begin // `R8G8B8A8:
+//                 sampled_r[31:24] = R;
+//                 sampled_r[23:16] = R;
+//                 sampled_r[15:8]  = G;
+//                 sampled_r[7:0]   = A;
+//             end
+//         endcase
+//     end
+
+//     assign texel_sampled = sampled_r;
+
+// endmodule
+
 
-endmodule
\ No newline at end of file
diff --git a/hw/rtl/tex_unit/VX_tex_sampler.v b/hw/rtl/tex_unit/VX_tex_sampler.v
index bb7fdb79..eee2ff5f 100644
--- a/hw/rtl/tex_unit/VX_tex_sampler.v
+++ b/hw/rtl/tex_unit/VX_tex_sampler.v
@@ -33,47 +33,71 @@ module VX_tex_sampler #(
     
     `UNUSED_PARAM (CORE_ID)
 
+    wire [31:0] req_data [`NUM_THREADS-1:0];
 
     if (req_filter == 0) begin // point sampling
-    
-        wire [31:0] req_data [`NUM_THREADS-1:0];
 
         for (genvar i = 0; i<`NUM_THREADS ;i++ ) begin
-            
+            req_data[i] = req_texels[i][0]
+        end
+
+    end else begin // bilinear sampling
+
+        for (genvar i = 0; i<`NUM_THREADS ;i++ ) begin
+
+            // wire [3:0][63:0]            formatted_data;
+            // wire [`TEX_FORMAT_BITS-1:0] color_enable;
+
             VX_tex_format #(
-                .CORE_ID (CORE_ID)
-            ) tex_format_point (
+                .CORE_ID (CORE_ID),
+                .NUM_TEXELS (4)
+            ) tex_format_texel (
                 .texel_data  (req_texels[i]),
                 .format (req_format),
 
-                .color_enable (),
-                .R(req_data[i][`RBEGIN +: 8]),
-                .G(req_data[i][`GBEGIN +: 8]),
-                .B(req_data[i][`BBEGIN +: 8]),
-                .A(req_data[i][`ABEGIN +: 8])
-            );       
+                .color_enable (color_enable),
+                .formatted_texel(formatted_data)
+            );  
+
+            //blendU/blendV calculation
+            wire [`BLEND_FRAC_64-1:0]      blendU;
+            wire [`BLEND_FRAC_64-1:0]      blendV;
+
+            assign blendU = req_u[i][`BLEND_FRAC_64-1:0];
+            assign blendV = req_v[i][`BLEND_FRAC_64-1:0];
+
+            VX_bilerp #(
+                .CORE_ID (CORE_ID)
+            ) tex_bilerp (
+                .blendU(blendU), //blendU
+                .blendV(blendV),  //blendV
+
+                .color_enable(color_enable),
+                .texels(formatted_data),
+
+                .sampled_data(req_data[i])
+            );    
 
         end
 
-        VX_pipe_register #(
-            .DATAW  (1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32)),
-            .RESETW (1)
-        ) pipe_reg (
-            .clk      (clk),
-            .reset    (reset),
-            .enable   (~stall_out),
-            .data_in  ({req_valid, req_wid, req_tmask, req_PC, req_rd, req_wb, req_data}),
-            .data_out ({rsp_valid, rsp_wid, rsp_tmask, rsp_PC, rsp_rd, rsp_wb, rsp_data})
-        );
-
-        // output
-        assign stall_out = ~rsp_ready;
-        assign req_ready = rsp_ready;
-
-    end else begin // bilinear sampling
-        // TO DO
     end
 
+    assign stall_out = ~rsp_ready;
+    assign req_ready = rsp_ready;     
+
+    VX_pipe_register #(
+        .DATAW  (1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32)),
+        .RESETW (1)
+    ) pipe_reg (
+        .clk      (clk),
+        .reset    (reset),
+        .enable   (~stall_out),
+        .data_in  ({req_valid, req_wid, req_tmask, req_PC, req_rd, req_wb, req_data}),
+        .data_out ({rsp_valid, rsp_wid, rsp_tmask, rsp_PC, rsp_rd, rsp_wb, rsp_data})
+    );
+
+
+
 
 
 endmodule
\ No newline at end of file