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minor update

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This commit is contained in:
Blaise Tine
2021-09-07 23:47:41 -07:00
parent 134cbcfc5a
commit c06efbf480
6 changed files with 25 additions and 32 deletions
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4
hw/rtl/libs/VX_index_buffer.v
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@@ -42,8 +42,8 @@ module VX_index_buffer #(
if (release_slot) begin
free_slots_n[release_addr] = 1;
end
if (acquire_slot) begin
free_slots_n[write_addr_r] = 0;
if (acquire_slot) begin
free_slots_n[write_addr_r] = 0;
end
end

14
hw/rtl/libs/VX_pending_size.v
View File

@@ -7,8 +7,8 @@ module VX_pending_size #(
) (
input wire clk,
input wire reset,
input wire push,
input wire pop,
input wire incr,
input wire decr,
output wire empty,
output wire full,
output wire [SIZEW-1:0] size
@@ -25,19 +25,19 @@ module VX_pending_size #(
empty_r <= 1;
full_r <= 0;
end else begin
assert(!push || !full);
if (push) begin
if (!pop) begin
assert(!incr || !full);
if (incr) begin
if (!decr) begin
empty_r <= 0;
if (used_r == ADDRW'(SIZE-1))
full_r <= 1;
end
end else if (pop) begin
end else if (decr) begin
full_r <= 0;
if (used_r == ADDRW'(1))
empty_r <= 1;
end
used_r <= used_r + ADDRW'($signed(2'(push && !pop) - 2'(pop && !push)));
used_r <= used_r + ADDRW'($signed(2'(incr && !decr) - 2'(decr && !incr)));
end
end