debug tracing refactoring

2021-10-17 13:42:16 -07:00
parent af6d9e7a8b
commit bf72800676
26 changed files with 148 additions and 169 deletions
--- a/hw/rtl/cache/VX_bank.sv
+++ b/hw/rtl/cache/VX_bank.sv
@@ -509,7 +509,7 @@ module VX_bank #(
    assign perf_mshr_stalls  = mshr_alm_full;
 `endif

-`ifdef DBG_PRINT_CACHE_BANK
+`ifdef DBG_TRACE_CACHE_BANK
    wire crsq_fire = crsq_valid && crsq_ready;
    wire pipeline_stall = (mshr_valid || mem_rsp_valid || creq_valid) 
                       && ~(mshr_fire || mem_rsp_fire || creq_fire);