debug tracing refactoring

2021-10-17 13:42:16 -07:00
parent af6d9e7a8b
commit bf72800676
26 changed files with 148 additions and 169 deletions
--- a/hw/rtl/VX_lsu_unit.sv
+++ b/hw/rtl/VX_lsu_unit.sv
@@ -330,7 +330,7 @@ module VX_lsu_unit #(
    end
 `endif
    
-`ifdef DBG_PRINT_CORE_DCACHE
+`ifdef DBG_TRACE_CORE_DCACHE
    wire dcache_req_fire_any = (| dcache_req_fire);
    always @(posedge clk) begin    
        if (lsu_req_if.valid && fence_wait) begin