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yosys synthesis refactoring

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This commit is contained in:
Blaise Tine
2020-07-10 18:56:41 -04:00
parent 77c3b2d45f
commit bdfacf709c
28 changed files with 136 additions and 134 deletions
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10
hw/rtl/libs/VX_matrix_arbiter.v
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@@ -1,7 +1,7 @@
`include "VX_define.vh"
module VX_matrix_arbiter #(
parameter N = 0
parameter N = 1
) (
input wire clk,
input wire reset,
@@ -27,8 +27,8 @@ module VX_matrix_arbiter #(
genvar i, j;
for (i = 0; i < N; ++i) begin
for (j = 0; j < N; ++j) begin
for (i = 0; i < N; i++) begin
for (j = 0; j < N; j++) begin
if (j > i) begin
assign pri[j][i] = requests[i] && state[i][j];
end
@@ -43,8 +43,8 @@ module VX_matrix_arbiter #(
assign grant_onehot[i] = requests[i] && !(| pri[i]);
end
for (i = 0; i < N; ++i) begin
for (j = i + 1; j < N; ++j) begin
for (i = 0; i < N; i++) begin
for (j = i + 1; j < N; j++) begin
always @(posedge clk) begin
if (reset) begin
state[i][j] <= 0;