yosys synthesis refactoring

hw/rtl/libs/VX_encoder_onehot.v

@@ -3,20 +3,19 @@
 module VX_encoder_onehot #(
     parameter N = 6
 ) (
-    input wire [N-1:0] onehot,
-    output reg valid,
-    output reg [`LOG2UP(N)-1:0] value
+    input wire [N-1:0] onehot,    
+    output reg [`LOG2UP(N)-1:0] binary,
+    output reg valid
 );
     integer i;
 
     always @(*) begin
         valid = 1'b0;    
-        value = {`LOG2UP(N){1'bx}};                
+        binary = `LOG2UP(N)'(0);                
         for (i = 0; i < N; i++) begin
             if (onehot[i]) begin
                 valid = 1'b1;
-                value = `LOG2UP(N)'(i);
-                break;
+                binary = `LOG2UP(N)'(i);
             end
         end
     end