wu-arch/kernels
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

yosys synthesis refactoring

Browse Source
This commit is contained in:
Blaise Tine
2020-07-10 18:56:41 -04:00
parent 77c3b2d45f
commit bdfacf709c
28 changed files with 136 additions and 134 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
hw/modelsim/Makefile
View File

@@ -69,8 +69,8 @@ SRC = \
../rtl/cache/VX_generic_pe.v \
../rtl/cache/cache_set.v \
../rtl/cache/VX_cache_data_per_index.v \
../rtl/pipe_regs/VX_d_e_reg.v \
../rtl/pipe_regs/VX_f_d_reg.v \
../rtl/VX_d_e_reg.v \
../rtl/VX_f_d_reg.v \
../models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v \
../models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.v \
../models/memory/cln28hpm/rf2_256x19_wm0/rf2_256x19_wm0.v \