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minor update

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This commit is contained in:
Blaise Tine
2021-08-03 01:13:18 -07:00
parent 7b921387bc
commit bd433b55b0
4 changed files with 12 additions and 10 deletions
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2
hw/rtl/VX_execute.v
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@@ -96,7 +96,7 @@ module VX_execute #(
.LANES (`NUM_THREADS), .LANES (`NUM_THREADS),
.DATA_SIZE (4), .DATA_SIZE (4),
.TAG_IN_WIDTH (`LSU_TEX_DCACHE_TAG_BITS), .TAG_IN_WIDTH (`LSU_TEX_DCACHE_TAG_BITS),
.TAG_SEL_IDX (2) .TAG_SEL_IDX (`NC_ADDR_BITS + `SM_ENABLE)
) tex_lsu_arb ( ) tex_lsu_arb (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),

1
hw/rtl/VX_lsu_unit.v
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@@ -131,6 +131,7 @@ module VX_lsu_unit #(
wire mbuf_pop = dcache_rsp_fire && (0 == rsp_rem_mask_n); wire mbuf_pop = dcache_rsp_fire && (0 == rsp_rem_mask_n);
assign mbuf_raddr = dcache_rsp_if.tag[ADDR_TYPEW +: `LSUQ_ADDR_BITS]; assign mbuf_raddr = dcache_rsp_if.tag[ADDR_TYPEW +: `LSUQ_ADDR_BITS];
`UNUSED_VAR (dcache_rsp_if.tag)
VX_index_buffer #( VX_index_buffer #(
.DATAW (`NW_BITS + 32 + `NUM_THREADS + `NR_BITS + 1 + `LSU_BITS + (`NUM_THREADS * REQ_ASHIFT) + 1), .DATAW (`NW_BITS + 32 + `NUM_THREADS + `NR_BITS + 1 + `LSU_BITS + (`NUM_THREADS * REQ_ASHIFT) + 1),

8
hw/rtl/VX_mem_unit.v
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@@ -188,13 +188,13 @@ module VX_mem_unit # (
VX_dcache_req_if #( VX_dcache_req_if #(
.NUM_REQS (`DNUM_REQS), .NUM_REQS (`DNUM_REQS),
.WORD_SIZE (`DWORD_SIZE), .WORD_SIZE (`DWORD_SIZE),
.TAG_WIDTH (`DCORE_TAG_WIDTH-`SM_ENABLE) .TAG_WIDTH (`DCORE_TAG_WIDTH-1)
) smem_req_if(); ) smem_req_if();
VX_dcache_rsp_if #( VX_dcache_rsp_if #(
.NUM_REQS (`DNUM_REQS), .NUM_REQS (`DNUM_REQS),
.WORD_SIZE (`DWORD_SIZE), .WORD_SIZE (`DWORD_SIZE),
.TAG_WIDTH (`DCORE_TAG_WIDTH-`SM_ENABLE) .TAG_WIDTH (`DCORE_TAG_WIDTH-1)
) smem_rsp_if(); ) smem_rsp_if();
VX_smem_arb #( VX_smem_arb #(
@@ -252,8 +252,8 @@ module VX_mem_unit # (
.NUM_REQS (`SNUM_REQS), .NUM_REQS (`SNUM_REQS),
.CREQ_SIZE (`SCREQ_SIZE), .CREQ_SIZE (`SCREQ_SIZE),
.CRSQ_SIZE (`SCRSQ_SIZE), .CRSQ_SIZE (`SCRSQ_SIZE),
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH-`SM_ENABLE), .CORE_TAG_WIDTH (`DCORE_TAG_WIDTH-1),
.CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS-`SM_ENABLE), .CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS-1),
.BANK_ADDR_OFFSET (`SBANK_ADDR_OFFSET) .BANK_ADDR_OFFSET (`SBANK_ADDR_OFFSET)
) smem ( ) smem (
.clk (clk), .clk (clk),

5
hw/rtl/tex_unit/VX_tex_memory.v
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@@ -167,6 +167,7 @@ module VX_tex_memory #(
wire rsp_texel_dup; wire rsp_texel_dup;
assign rsp_texel_idx = dcache_rsp_if.tag[1:0]; assign rsp_texel_idx = dcache_rsp_if.tag[1:0];
`UNUSED_VAR (dcache_rsp_if.tag)
assign rsp_texel_dup = q_dup_reqs[rsp_texel_idx]; assign rsp_texel_dup = q_dup_reqs[rsp_texel_idx];
@@ -266,13 +267,13 @@ module VX_tex_memory #(
always @(posedge clk) begin always @(posedge clk) begin
if (dcache_req_fire_any) begin if (dcache_req_fire_any) begin
$write("%t: core%0d-tex-cache-req: wid=%0d, PC=%0h, tmask=%b, tag=%0h, addr=", $write("%t: core%0d-tex-cache-req: wid=%0d, PC=%0h, tmask=%b, tag=%0h, addr=",
$time, CORE_ID, q_req_wid, q_req_PC, dcache_req_fire, dcache_req_if.tag[0]); $time, CORE_ID, q_req_wid, q_req_PC, dcache_req_fire, req_texel_idx);
`PRINT_ARRAY1D(req_texel_addr, NUM_REQS); `PRINT_ARRAY1D(req_texel_addr, NUM_REQS);
$write(", is_dup=%b\n", req_texel_dup); $write(", is_dup=%b\n", req_texel_dup);
end end
if (dcache_rsp_fire) begin if (dcache_rsp_fire) begin
$write("%t: core%0d-tex-cache-rsp: wid=%0d, PC=%0h, tmask=%b, tag=%0h, data=", $write("%t: core%0d-tex-cache-rsp: wid=%0d, PC=%0h, tmask=%b, tag=%0h, data=",
$time, CORE_ID, q_req_wid, q_req_PC, dcache_rsp_if.tmask, dcache_rsp_if.tag); $time, CORE_ID, q_req_wid, q_req_PC, dcache_rsp_if.tmask, rsp_texel_idx);
`PRINT_ARRAY1D(dcache_rsp_if.data, NUM_REQS); `PRINT_ARRAY1D(dcache_rsp_if.data, NUM_REQS);
$write("\n"); $write("\n");
end end