Demo SOC W=8, T=4 Passing

2020-03-30 22:17:38 -07:00
parent 66a837b0df
commit bcf894b581
3 changed files with 6 additions and 2 deletions
--- a/rtl/VX_cache/VX_bank.v
+++ b/rtl/VX_cache/VX_bank.v
@@ -468,6 +468,7 @@ module VX_bank
 		.clk           (clk),
 		.reset         (reset),
 		.stall         (stall_bank_pipe),
+		.stall_bank_pipe(stall_bank_pipe),

 		// Initial Read
 		.readaddr_st10 (addr_st1[0]),