rebase master update
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Blaise Tine
226
hw/rtl/tex_unit/VX_tex_unit.v
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226
hw/rtl/tex_unit/VX_tex_unit.v
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`include "VX_tex_define.vh"
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module VX_tex_unit #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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// Texture unit <-> Memory Unit
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VX_dcache_req_if dcache_req_if,
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VX_dcache_rsp_if dcache_rsp_if,
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// Inputs
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VX_tex_req_if tex_req_if,
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VX_tex_csr_if tex_csr_if,
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// Outputs
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VX_tex_rsp_if tex_rsp_if
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);
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localparam REQ_INFO_WIDTH_S = `NR_BITS + 1 + `NW_BITS + 32;
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localparam REQ_INFO_WIDTH_A = `TEX_FORMAT_BITS + REQ_INFO_WIDTH_S;
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localparam REQ_INFO_WIDTH_M = (2 * `NUM_THREADS * `BLEND_FRAC) + REQ_INFO_WIDTH_A;
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reg [`TEX_MIPOFF_BITS-1:0] tex_mipoff [`NUM_TEX_UNITS-1:0][(1 << `TEX_LOD_BITS)-1:0];
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reg [`TEX_DIM_BITS-1:0] tex_dims [1:0][`NUM_TEX_UNITS-1:0][(1 << `TEX_LOD_BITS)-1:0];
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reg [`TEX_ADDR_BITS-1:0] tex_baddr [`NUM_TEX_UNITS-1:0];
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reg [`TEX_FORMAT_BITS-1:0] tex_format [`NUM_TEX_UNITS-1:0];
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reg [`TEX_WRAP_BITS-1:0] tex_wraps [1:0][`NUM_TEX_UNITS-1:0];
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reg [`TEX_FILTER_BITS-1:0] tex_filter [`NUM_TEX_UNITS-1:0];
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// CSRs programming
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for (genvar i = 0; i < `NUM_TEX_UNITS; ++i) begin
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wire [`TEX_LOD_BITS-1:0] mip_level = tex_csr_if.write_data[28 +: `TEX_LOD_BITS];
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always @(posedge clk) begin
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if (tex_csr_if.write_enable) begin
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case (tex_csr_if.write_addr)
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`CSR_TEX_ADDR(i) : begin
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tex_baddr[i] <= tex_csr_if.write_data[`TEX_ADDR_BITS-1:0];
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end
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`CSR_TEX_FORMAT(i) : begin
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tex_format[i] <= tex_csr_if.write_data[`TEX_FORMAT_BITS-1:0];
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end
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`CSR_TEX_WRAP(i) : begin
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tex_wraps[0][i] <= tex_csr_if.write_data[0 +: `TEX_WRAP_BITS];
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tex_wraps[1][i] <= tex_csr_if.write_data[`TEX_WRAP_BITS +: `TEX_WRAP_BITS];
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end
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`CSR_TEX_FILTER(i) : begin
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tex_filter[i] <= tex_csr_if.write_data[`TEX_FILTER_BITS-1:0];
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end
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`CSR_TEX_MIPOFF(i) : begin
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tex_mipoff[i][mip_level] <= tex_csr_if.write_data[`TEX_MIPOFF_BITS-1:0];
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end
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`CSR_TEX_WIDTH(i) : begin
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tex_dims[0][i][mip_level] <= tex_csr_if.write_data[`TEX_DIM_BITS-1:0];
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end
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`CSR_TEX_HEIGHT(i) : begin
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tex_dims[1][i][mip_level] <= tex_csr_if.write_data[`TEX_DIM_BITS-1:0];
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end
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endcase
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end
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end
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end
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// mipmap attributes
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wire [`NUM_THREADS-1:0][`TEX_MIPOFF_BITS-1:0] sel_mipoff;
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wire [1:0][`NUM_THREADS-1:0][`TEX_DIM_BITS-1:0] sel_dims;
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for (genvar i = 0; i < `NUM_THREADS; ++i) begin
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wire [`NTEX_BITS-1:0] unit = tex_req_if.unit[`NTEX_BITS-1:0];
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wire [`TEX_LOD_BITS-1:0] mip_level = tex_req_if.lod[i][20+:`TEX_LOD_BITS];
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assign sel_mipoff[i] = tex_mipoff[unit][mip_level];
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assign sel_dims[0][i] = tex_dims[0][unit][mip_level];
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assign sel_dims[1][i] = tex_dims[1][unit][mip_level];
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end
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// address generation
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wire mem_req_valid;
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wire [`NUM_THREADS-1:0] mem_req_tmask;
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wire [`TEX_FILTER_BITS-1:0] mem_req_filter;
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wire [`TEX_STRIDE_BITS-1:0] mem_req_stride;
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wire [1:0][`NUM_THREADS-1:0][`BLEND_FRAC-1:0] mem_req_blends;
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wire [`NUM_THREADS-1:0][3:0][31:0] mem_req_addr;
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wire [REQ_INFO_WIDTH_A-1:0] mem_req_info;
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wire mem_req_ready;
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VX_tex_addr #(
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.CORE_ID (CORE_ID),
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.REQ_INFO_WIDTH (REQ_INFO_WIDTH_A),
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.NUM_REQS (`NUM_THREADS)
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) tex_addr (
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.clk (clk),
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.reset (reset),
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.req_valid (tex_req_if.valid),
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.req_tmask (tex_req_if.tmask),
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.req_coords (tex_req_if.coords),
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.req_format (tex_format[tex_req_if.unit]),
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.req_filter (tex_filter[tex_req_if.unit]),
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.req_wraps ({tex_wraps[1][tex_req_if.unit], tex_wraps[0][tex_req_if.unit]}),
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.req_baseaddr(tex_baddr[tex_req_if.unit]),
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.req_mipoffset(sel_mipoff),
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.req_logdims(sel_dims),
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.req_info ({tex_format[tex_req_if.unit], tex_req_if.rd, tex_req_if.wb, tex_req_if.wid, tex_req_if.PC}),
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.req_ready (tex_req_if.ready),
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.rsp_valid (mem_req_valid),
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.rsp_tmask (mem_req_tmask),
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.rsp_filter (mem_req_filter),
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.rsp_stride (mem_req_stride),
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.rsp_addr (mem_req_addr),
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.rsp_blends (mem_req_blends),
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.rsp_info (mem_req_info),
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.rsp_ready (mem_req_ready)
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);
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// retrieve texel values from memory
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wire mem_rsp_valid;
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wire [`NUM_THREADS-1:0] mem_rsp_tmask;
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wire [`NUM_THREADS-1:0][3:0][31:0] mem_rsp_data;
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wire [REQ_INFO_WIDTH_M-1:0] mem_rsp_info;
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wire mem_rsp_ready;
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VX_tex_memory #(
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.CORE_ID (CORE_ID),
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.REQ_INFO_WIDTH (REQ_INFO_WIDTH_M),
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.NUM_REQS (`NUM_THREADS)
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) tex_memory (
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.clk (clk),
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.reset (reset),
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// memory interface
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.dcache_req_if (dcache_req_if),
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.dcache_rsp_if (dcache_rsp_if),
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// inputs
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.req_valid (mem_req_valid),
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.req_tmask (mem_req_tmask),
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.req_filter(mem_req_filter),
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.req_stride(mem_req_stride),
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.req_addr (mem_req_addr),
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.req_info ({mem_req_blends, mem_req_info}),
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.req_ready (mem_req_ready),
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// outputs
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.rsp_valid (mem_rsp_valid),
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.rsp_tmask (mem_rsp_tmask),
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.rsp_data (mem_rsp_data),
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.rsp_info (mem_rsp_info),
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.rsp_ready (mem_rsp_ready)
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);
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// apply sampler
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wire [`NUM_THREADS-1:0][1:0][`BLEND_FRAC-1:0] rsp_blends;
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wire [`TEX_FORMAT_BITS-1:0] rsp_format;
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wire [REQ_INFO_WIDTH_S-1:0] rsp_info;
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assign {rsp_blends, rsp_format, rsp_info} = mem_rsp_info;
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VX_tex_sampler #(
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.CORE_ID (CORE_ID),
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.REQ_INFO_WIDTH (REQ_INFO_WIDTH_S),
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.NUM_REQS (`NUM_THREADS)
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) tex_sampler (
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.clk (clk),
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.reset (reset),
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// inputs
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.req_valid (mem_rsp_valid),
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.req_tmask (mem_rsp_tmask),
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.req_data (mem_rsp_data),
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.req_format (rsp_format),
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.req_blends (rsp_blends),
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.req_info (rsp_info),
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.req_ready (mem_rsp_ready),
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// outputs
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.rsp_valid (tex_rsp_if.valid),
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.rsp_tmask (tex_rsp_if.tmask),
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.rsp_data (tex_rsp_if.data),
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.rsp_info ({tex_rsp_if.rd, tex_rsp_if.wb, tex_rsp_if.wid, tex_rsp_if.PC}),
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.rsp_ready (tex_rsp_if.ready)
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);
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`ifdef DBG_PRINT_TEX
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for (genvar i = 0; i < `NUM_TEX_UNITS; ++i) begin
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always @(posedge clk) begin
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if (tex_csr_if.write_enable
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&& (tex_csr_if.write_addr >= `CSR_TEX_BEGIN(i)
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&& tex_csr_if.write_addr < `CSR_TEX_BEGIN(i+1))) begin
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$display("%t: core%0d-tex-csr: tex%0d_addr=%0h", $time, CORE_ID, i, tex_baddr[i]);
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$display("%t: core%0d-tex-csr: tex%0d_format=%0h", $time, CORE_ID, i, tex_format[i]);
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$display("%t: core%0d-tex-csr: tex%0d_wrap_u=%0h", $time, CORE_ID, i, tex_wraps[0][i]);
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$display("%t: core%0d-tex-csr: tex%0d_wrap_v=%0h", $time, CORE_ID, i, tex_wraps[1][i]);
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$display("%t: core%0d-tex-csr: tex%0d_filter=%0h", $time, CORE_ID, i, tex_filter[i]);
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$display("%t: core%0d-tex-csr: tex%0d_mipoff[0]=%0h", $time, CORE_ID, i, tex_mipoff[i][0]);
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$display("%t: core%0d-tex-csr: tex%0d_width[0]=%0h", $time, CORE_ID, i, tex_dims[0][i][0]);
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$display("%t: core%0d-tex-csr: tex%0d_height[0]=%0h", $time, CORE_ID, i, tex_dims[1][i][0]);
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end
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end
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end
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always @(posedge clk) begin
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if (tex_req_if.valid && tex_req_if.ready) begin
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$display("%t: core%0d-tex-req: wid=%0d, PC=%0h, tmask=%b, unit=%0d, lod=%0h, u=",
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$time, CORE_ID, tex_req_if.wid, tex_req_if.PC, tex_req_if.tmask, tex_req_if.unit, tex_req_if.lod);
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`PRINT_ARRAY1D(tex_req_if.coords[0], `NUM_THREADS);
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$write(", v=");
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`PRINT_ARRAY1D(tex_req_if.coords[1], `NUM_THREADS);
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$write("\n");
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end
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if (tex_rsp_if.valid && tex_rsp_if.ready) begin
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$write("%t: core%0d-tex-rsp: wid=%0d, PC=%0h, tmask=%b, data=",
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$time, CORE_ID, tex_rsp_if.wid, tex_rsp_if.PC, tex_rsp_if.tmask);
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`PRINT_ARRAY1D(tex_rsp_if.data, `NUM_THREADS);
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$write("\n");
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end
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end
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`endif
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endmodule
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