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cache refactoring - phase 2

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This commit is contained in:
Blaise Tine
2020-11-03 04:51:40 -08:00
parent 5be1d85648
commit ba81d76e02
19 changed files with 567 additions and 424 deletions
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38
hw/rtl/cache/VX_cache_dram_req_arb.v vendored
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@@ -2,11 +2,11 @@
module VX_cache_dram_req_arb #(
// Size of line inside a bank in bytes
parameter BANK_LINE_SIZE = 0,
// Number of banks {1, 2, 4, 8,...}
parameter NUM_BANKS = 0,
parameter BANK_LINE_SIZE = 1,
// Number of banks
parameter NUM_BANKS = 1,
// Size of a word in bytes
parameter WORD_SIZE = 0
parameter WORD_SIZE = 1
) (
input wire clk,
input wire reset,
@@ -28,28 +28,36 @@ module VX_cache_dram_req_arb #(
input wire dram_req_ready
);
wire [`BANK_BITS-1:0] sel_bank;
wire sel_valid;
wire [`BANK_BITS-1:0] sel_idx;
wire [NUM_BANKS-1:0] sel_1hot;
VX_fixed_arbiter #(
.N(NUM_BANKS)
) sel_arb (
.clk (clk),
.reset (reset),
.requests (per_bank_dram_req_valid),
.grant_index (sel_bank),
.requests (per_bank_dram_req_valid),
.grant_valid (sel_valid),
`UNUSED_PIN (grant_onehot)
.grant_index (sel_idx),
.grant_onehot(sel_1hot)
);
assign dram_req_valid = sel_valid;
assign dram_req_rw = per_bank_dram_req_rw[sel_bank];
assign dram_req_byteen = per_bank_dram_req_byteen[sel_bank];
assign dram_req_addr = per_bank_dram_req_addr[sel_bank];
assign dram_req_data = per_bank_dram_req_data[sel_bank];
wire stall = ~dram_req_ready && dram_req_valid;
VX_generic_register #(
.N(1 + 1 + BANK_LINE_SIZE + `DRAM_ADDR_WIDTH + `BANK_LINE_WIDTH)
) core_wb_reg (
.clk (clk),
.reset (reset),
.stall (stall),
.flush (1'b0),
.in ({sel_valid, per_bank_dram_req_rw[sel_idx], per_bank_dram_req_byteen[sel_idx], per_bank_dram_req_addr[sel_idx], per_bank_dram_req_data[sel_idx]}),
.out ({dram_req_valid, dram_req_rw, dram_req_byteen, dram_req_addr, dram_req_data})
);
for (genvar i = 0; i < NUM_BANKS; i++) begin
assign per_bank_dram_req_ready[i] = dram_req_ready && (sel_bank == `BANK_BITS'(i));
assign per_bank_dram_req_ready[i] = sel_1hot[i] && !stall;
end
endmodule