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cache refactoring - phase 2

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This commit is contained in:
Blaise Tine
2020-11-03 04:51:40 -08:00
parent 5be1d85648
commit ba81d76e02
19 changed files with 567 additions and 424 deletions
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20
hw/rtl/VX_mem_unit.v
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@@ -65,13 +65,15 @@ module VX_mem_unit # (
.NUM_REQUESTS (`SNUM_REQUESTS),
.CREQ_SIZE (`SCREQ_SIZE),
.MRVQ_SIZE (8),
.DRPQ_SIZE (1),
.DRFQ_SIZE (1),
.SNRQ_SIZE (1),
.CWBQ_SIZE (`SCWBQ_SIZE),
.DREQ_SIZE (1),
.SNOOP_FORWARDING (0),
.SNPQ_SIZE (1),
.DRAM_ENABLE (0),
.FLUSH_ENABLE (0),
.WRITE_ENABLE (1),
.SNOOP_FORWARDING (0),
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH),
.CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS),
.DRAM_TAG_WIDTH (`SDRAM_TAG_WIDTH)
@@ -145,13 +147,15 @@ module VX_mem_unit # (
.NUM_REQUESTS (`DNUM_REQUESTS),
.CREQ_SIZE (`DCREQ_SIZE),
.MRVQ_SIZE (`DMRVQ_SIZE),
.DRPQ_SIZE (`DDRPQ_SIZE),
.DRFQ_SIZE (`DDRFQ_SIZE),
.SNRQ_SIZE (`DSNRQ_SIZE),
.CWBQ_SIZE (`DCWBQ_SIZE),
.DREQ_SIZE (`DDREQ_SIZE),
.SNOOP_FORWARDING (0),
.DREQ_SIZE (`DDREQ_SIZE),
.SNPQ_SIZE (`DSNPQ_SIZE),
.DRAM_ENABLE (1),
.FLUSH_ENABLE (1),
.WRITE_ENABLE (1),
.SNOOP_FORWARDING (0),
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH),
.CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS),
.DRAM_TAG_WIDTH (`DDRAM_TAG_WIDTH),
@@ -226,13 +230,15 @@ module VX_mem_unit # (
.NUM_REQUESTS (`INUM_REQUESTS),
.CREQ_SIZE (`ICREQ_SIZE),
.MRVQ_SIZE (`IMRVQ_SIZE),
.DRPQ_SIZE (`IDRPQ_SIZE),
.DRFQ_SIZE (`IDRFQ_SIZE),
.SNRQ_SIZE (1),
.CWBQ_SIZE (`ICWBQ_SIZE),
.DREQ_SIZE (`IDREQ_SIZE),
.SNOOP_FORWARDING (0),
.SNPQ_SIZE (1),
.DRAM_ENABLE (1),
.FLUSH_ENABLE (0),
.WRITE_ENABLE (0),
.SNOOP_FORWARDING (0),
.CORE_TAG_WIDTH (`ICORE_TAG_WIDTH),
.CORE_TAG_ID_BITS (`ICORE_TAG_ID_BITS),
.DRAM_TAG_WIDTH (`IDRAM_TAG_WIDTH)