RTL code refactoring

2020-04-21 01:03:37 -04:00
parent cfa8626bf7
commit ba4e736782
29 changed files with 332 additions and 563 deletions
--- a/hw/rtl/pipe_regs/VX_d_e_reg.v
+++ b/hw/rtl/pipe_regs/VX_d_e_reg.v
@@ -3,14 +3,14 @@
 module VX_d_e_reg (
 	input wire        		clk,
 	input wire              reset,
-	input wire              branch_stall_i,
-	input wire              freeze_i,
+	input wire              branch_stall,
+	input wire              freeze,
 	VX_frE_to_bckE_req_if 	frE_to_bckE_req_if,
 	VX_frE_to_bckE_req_if	bckE_req_if
 );

-	wire stall = freeze_i;
-	wire flush = (branch_stall_i == `STALL);
+	wire stall = freeze;
+	wire flush = (branch_stall == `STALL);

 	VX_generic_register #(
 		.N(233 + `NW_BITS-1 + 1 + `NUM_THREADS)