RTL code refactoring
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24
hw/rtl/cache/VX_cache_req_queue.v
vendored
24
hw/rtl/cache/VX_cache_req_queue.v
vendored
@@ -56,21 +56,21 @@ module VX_cache_req_queue #(
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input wire [31:0] bank_pc,
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// Dequeue Data
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input wire reqq_pop,
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output wire reqq_req_st0,
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input wire reqq_pop,
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output wire reqq_req_st0,
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output wire [`LOG2UP(NUM_REQUESTS)-1:0] reqq_req_tid_st0,
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output wire [31:0] reqq_req_addr_st0,
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output wire [`WORD_SIZE_RNG] reqq_req_writedata_st0,
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output wire [4:0] reqq_req_rd_st0,
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output wire [1:0] reqq_req_wb_st0,
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output wire [`NW_BITS-1:0] reqq_req_warp_num_st0,
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output wire [2:0] reqq_req_mem_read_st0,
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output wire [2:0] reqq_req_mem_write_st0,
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output wire [31:0] reqq_req_pc_st0,
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output wire [31:0] reqq_req_addr_st0,
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output wire [`WORD_SIZE_RNG] reqq_req_writedata_st0,
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output wire [4:0] reqq_req_rd_st0,
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output wire [1:0] reqq_req_wb_st0,
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output wire [`NW_BITS-1:0] reqq_req_warp_num_st0,
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output wire [2:0] reqq_req_mem_read_st0,
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output wire [2:0] reqq_req_mem_write_st0,
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output wire [31:0] reqq_req_pc_st0,
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// State Data
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output wire reqq_empty,
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output wire reqq_full
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output wire reqq_empty,
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output wire reqq_full
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);
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wire [NUM_REQUESTS-1:0] out_per_valids;
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