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rtl refactoring

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This commit is contained in:
Blaise Tine
2020-05-05 10:46:48 -04:00
parent f142afac80
commit b7e892ee16
39 changed files with 393 additions and 425 deletions
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8
hw/rtl/cache/VX_cache_miss_resrv.v vendored
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@@ -90,10 +90,10 @@ module VX_cache_miss_resrv #(
wire [`LOG2UP(MRVQ_SIZE)-1:0] enqueue_index = tail_ptr;
reg [MRVQ_SIZE-1:0] make_ready;
genvar curr_e;
genvar i;
generate
for (curr_e = 0; curr_e < MRVQ_SIZE; curr_e=curr_e+1) begin
assign make_ready[curr_e] = is_fill_st1 && valid_table[curr_e] && (addr_table[curr_e] == fill_addr_st1);
for (i = 0; i < MRVQ_SIZE; i=i+1) begin
assign make_ready[i] = is_fill_st1 && valid_table[i] && (addr_table[i] == fill_addr_st1);
end
endgenerate
@@ -107,7 +107,7 @@ module VX_cache_miss_resrv #(
wire mrvq_push = miss_add && enqueue_possible && (MRVQ_SIZE != 2);
wire mrvq_pop = miss_resrv_pop && dequeue_possible;
wire update_ready = (|make_ready);
wire update_ready = (| make_ready);
always @(posedge clk) begin
if (reset) begin