rtl refactoring
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@@ -15,8 +15,7 @@ module VX_front_end (
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VX_branch_rsp_if branch_rsp_if,
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VX_frE_to_bckE_req_if bckE_req_if,
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output wire fetch_ebreak
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output wire busy
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);
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VX_inst_meta_if fe_inst_meta_fi();
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@@ -29,18 +28,13 @@ module VX_front_end (
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wire total_freeze = schedule_delay;
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wire icache_stage_delay;
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wire vortex_ebreak;
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wire terminate_sim;
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wire[`NW_BITS-1:0] icache_stage_wid;
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wire[`NUM_THREADS-1:0] icache_stage_valids;
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wire[`NUM_THREADS-1:0] icache_stage_valids;
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assign fetch_ebreak = vortex_ebreak || terminate_sim;
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VX_wstall_if wstall_if();
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VX_join_if join_if();
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VX_wstall_if wstall_if();
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VX_join_if join_if();
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VX_fetch fetch(
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VX_fetch fetch (
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.clk (clk),
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.reset (reset),
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.icache_stage_wid (icache_stage_wid),
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@@ -52,7 +46,7 @@ module VX_front_end (
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.warp_ctl_if (warp_ctl_if),
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.icache_stage_delay (icache_stage_delay),
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.branch_rsp_if (branch_rsp_if),
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.ebreak (vortex_ebreak), // fetch_ebreak
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.busy (busy),
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.fe_inst_meta_fi (fe_inst_meta_fi)
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);
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@@ -91,9 +85,8 @@ module VX_front_end (
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.fd_inst_meta_de (fd_inst_meta_de),
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.frE_to_bckE_req_if (frE_to_bckE_req_if),
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.wstall_if (wstall_if),
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.join_if (join_if),
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.terminate_sim (terminate_sim)
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);
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.join_if (join_if)
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);
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wire no_br_stall = 0;
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