fixed assertion in lsu_unit

hw/simulate/Makefile

@@ -3,16 +3,17 @@
 MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2
 
 # control RTL debug print states
-DBG_PRINT_FLAGS = -DDBG_PRINT_CORE_ICACHE \
-				  -DDBG_PRINT_CORE_DCACHE \
-			      -DDBG_PRINT_CACHE_BANK  \
-				  -DDBG_PRINT_CACHE_SNP   \
-				  -DDBG_PRINT_CACHE_MSRQ  \
-				  -DDBG_PRINT_DRAM        \
-				  -DDBG_PRINT_PIPELINE    \
-				  -DDBG_PRINT_OPAE
+DBG_PRINT_FLAGS += -DDBG_PRINT_CORE_ICACHE
+DBG_PRINT_FLAGS += -DDBG_PRINT_CORE_DCACHE
+DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_BANK 
+DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_SNP 
+DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_MSRQ
+DBG_PRINT_FLAGS += -DDBG_PRINT_DRAM      
+DBG_PRINT_FLAGS += -DDBG_PRINT_PIPELINE  
+DBG_PRINT_FLAGS += -DDBG_PRINT_OPAE
 
-#DBG_PRINT=$(DBG_PRINT_FLAGS)
+#DBG_FLAGS += $(DBG_PRINT_FLAGS)
+#DBG_FLAGS += -DDBG_CORE_REQ_INFO
 
 INCLUDE = -I../rtl/ -I../rtl/libs -I../rtl/interfaces -I../rtl/pipe_regs -I../rtl/cache -I../rtl/simulate
 
@@ -27,7 +28,7 @@ VF += -Wno-DECLFILENAME
 VF += --x-initial unique
 VF += -exe $(SRCS) $(INCLUDE)
 
-DBG += -DVCD_OUTPUT $(DBG_PRINT)
+DBG += -DVCD_OUTPUT $(DBG_FLAGS)
 DBG += -DDBG_CORE_REQ_INFO
 
 THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))')

hw/simulate/simulator.cpp

@@ -13,6 +13,10 @@ Simulator::Simulator() {
   // force random values for unitialized signals  
   Verilated::randReset(2);
 
+#ifdef NDEBUG
+  Verilated::assertOn(false);
+#endif
+
   ram_ = nullptr;
   vortex_ = new VVortex();